公开(公告)号：EP0961269A1

公开(公告)日：1999-12-01

申请号：EP98830259.2

申请日：1998-04-29

Applicant: STMicroelectronics S.r.l.

Inventor： Bollati, Giacomino ,  Bruccoleri, Melchiorre ,  Portaluri, Salvatore ,  Celant, Luca

IPC: G11B20/00 ,  G11B20/10 ,  G11B5/09

CPC classification number: G11B20/10046 ,  G11B2220/2516

Abstract: A method of equalizing a read channel of a mass memory device on a magnetic support, comprises attenuating the low frequencies of the spectrum of the analog signal originating from an electromagnetic read transducer without boosting the high frequency harmonic components of the spectrum. The low frequencies of the spectrum of the analog input signal are attenuated with a low pass filter of an order comprised between 6 and 8 and a boost is implemented by introducing in the transfer function of the filter two real and opposed zeroes without altering the group delay.

Abstract translation: 一种均衡磁性支架上的大容量存储器件的读取通道的方法包括衰减来自电磁读取换能器的模拟信号的频谱的低频，而不会增加频谱的高频谐波分量。 模拟输入信号的频谱的低频通过包含在6和8之间的阶数的低通滤波器衰减，并且通过在滤波器的传递函数中引入两个实数和相对的零来实现升压，而不改变组延迟 。

公开(公告)号：EP1424773B1

公开(公告)日：2007-01-24

申请号：EP02425734.7

申请日：2002-11-28

Applicant: STMicroelectronics S.r.l.

Inventor： Radice, Francesco ,  Bruccoleri, Melchiorre

IPC: H03H11/04 ,  H03H11/48

CPC classification number: H03H11/0405 ,  H03H11/481

公开(公告)号：EP0776091B1

公开(公告)日：2003-02-12

申请号：EP95830487.5

申请日：1995-11-23

Applicant: STMicroelectronics S.r.l.

Inventor： Bruccoleri, Melchiorre ,  Cusinato, Paolo

IPC: H03K3/356

CPC classification number: H03K3/356156

公开(公告)号：EP0720112B1

公开(公告)日：2001-02-28

申请号：EP94830590.9

申请日：1994-12-27

Applicant: STMicroelectronics S.r.l. ,  Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe

Inventor： Bruccoleri, Melchiorre ,  Cosentino, Gaetano ,  Demicheli, Marco ,  Portaluri, Salvatore

IPC: G06G7/163

CPC classification number: G06G7/163

公开(公告)号：EP0892499B1

公开(公告)日：2000-09-27

申请号：EP97830351.9

申请日：1997-07-14

Applicant: STMicroelectronics S.r.l.

Inventor： Celant, Luca ,  De Micheli, Marco ,  Bruccoleri, Melchiorre ,  Rigazio, Luca

IPC: H03L7/07 ,  G11B20/10

CPC classification number: H03L7/07 ,  G11B20/1403

公开(公告)号：EP1014573A1

公开(公告)日：2000-06-28

申请号：EP98830760.9

申请日：1998-12-17

Applicant: STMicroelectronics S.r.l.

Inventor： Bollati, Giacomino ,  Alini, Roberto ,  Ottini, Daniele ,  Bruccoleri, Melchiorre

IPC: H03H11/04

CPC classification number: H03H11/0422

Abstract: A low pass filter with programmable equalization comprising at least a biquadratic cell (BIQUAD) and a converter of the input voltage (Vin) in a current ( iz ), proportional to the derivative of the input voltage, that is injected on a node of the biquadratic cell (BIQUAD) in order to introduce two real and opposed zeroes in the transfer function of the filter, is composed of two structurally similar circuits, functionally connected in cascade, each circuit being composed of a biquadratic cell and an input stage having two outputs injecting through a first current output (A) said current ( iz ) on an input capacitor (C1) of the respective biquadratic cell, by a direct coupling in a first of said two circuits and in an inverted manner in the second of said two circuits; a second voltage output (B) being coupled to an input of the respective biquadratic cell.

Abstract translation: 具有可编程均衡的低通滤波器，其包括至少一个二次电池（BIQUAD）和与输入电压的导数成比例的电流（iz）中的输入电压（Vin）的转换器，其被注入到 为了在滤波器的传递函数中引入两个实数和相对的零点，双级电容（BIQUAD）由两个结构相似的电路组成，功能上串联连接，每个电路由一个二次电池和一个具有两个输出的输入级组成 通过第一电流输出（A），通过在所述两个电路中的第一个中的直接耦合并且在所述两个电路中的第二个中以反向方式，在相应的二次电池的输入电容器（C1）上注入所述电流（iz） ; 第二电压输出（B）耦合到相应的双二次电池的输入端。

公开(公告)号：EP1006658A1

公开(公告)日：2000-06-07

申请号：EP98830727.8

申请日：1998-12-03

Applicant: STMicroelectronics S.r.l.

Inventor： Ottini, Daniele ,  Bruccoleri, Melchiorre ,  Marchese, Stefano ,  Bollati, Giacomino

IPC: H03K19/0175

CPC classification number: H03K19/017527

Abstract: A BiCMOS ECL/CMOS interface circuit for converting a high frequency pseudo-ECL signal with a voltage swing in the order of few hundreds of millivolts into a CMOS signal with a voltage swing substantially equal to the supply voltage, comprising a differential input stage composed of a pair of NPN bipolar junction transistors (Q1, Q2) in a common emitter configuration, a bias current generator (IBIAS) functionally coupled between the common emitter node of said NPN transistors and ground and means driven by a respective transistor of said input pair (Q1, Q2) driving the control node of a respective output CMOS stage (M5-M7, M6-M8), is provided with first and second common-collector stages each constituted by an NPN bipolar junction transistor(Q3, Q4) and driven by a respective transistor of said pair of NPN transistors (Q1, Q2); and with a pair of identical PMOS transistors (M1, M2) with gates connected in common to a bias voltage (POL), each PMOS transistor (M1, M2) having a source coupled to the emitter of a respective transistor (Q3, Q4) of said common-collector stages and a drain connected to a load current generator (I) and to said control node of a respective output CMOS stage (M5-M7, M6-M8), for reducing current absorption without impairing performance.

Abstract translation: 一种BiCMOS ECL / CMOS接口电路，用于将具有几百毫伏数量级的电压摆幅的高频伪ECL信号转换成具有基本上等于电源电压的电压摆幅的CMOS信号，包括差分输入级，其由 一个共同的发射结构的一对NPN双极结晶体管（Q1，Q2），功能上耦合在所述NPN晶体管的公共发射极节点与地之间的偏置电流发生器（IBIAS）和由所述输入对的相应晶体管驱动的装置 Q1，Q2）驱动各个输出CMOS级（M5-M7，M6-M8）的控制节点，设置有由NPN双极结型晶体管（Q3，Q4）构成的第一和第二公共集电极级，并由 所述一对NPN晶体管（Q1，Q2）的相应晶体管; 并且通过一对具有与偏置电压（POL）共同连接的栅极的一对相同的PMOS晶体管（M1，M2），每个PMOS晶体管（M1，M2）具有耦合到相应晶体管（Q3，Q4）的发射极的源极， 的所述共集电极级和连接到负载电流发生器（I）的漏极以及相应的输出CMOS级（M5-M7，M6-M8）的所述控制节点，用于减小电流吸收而不损害性能。

公开(公告)号：EP0957584A1

公开(公告)日：1999-11-17

申请号：EP98830300.4

申请日：1998-05-15

Applicant: STMicroelectronics S.r.l.

Inventor： Celant, Luca ,  Demicheli, Marco ,  Bruccoleri, Melchiorre ,  Ottini, Daniele

IPC: H03L7/089

CPC classification number: H03L7/0893 ,  H03L7/0896

Abstract: A phase locked ring comprising a phase comparator, a charge pumping circuit, a loop filter and a voltage controlled oscillator, where the loop filter comprises two input terminals connected with two symmetric branches of the charge pumping circuit, each symmetric branch comprising a constant current generator and a pulsed current generator. Feedback paths are provided to control constant current generators through the voltage available on both loop filter terminals. According to the present invention, pulsed current generators (I7, I8) are separated from the respective loop filter terminals (N1 , N2) by circuit breaking switching means (S1, S2), said circuit breaking switching means (S1, S2) being controlled by phase signals (UP, DOWN) outputted from the phase comparator (2).

Abstract translation: 一种锁相环，包括相位比较器，电荷泵浦电路，环路滤波器和压控振荡器，其中环路滤波器包括与电荷泵浦电路的两个对称分支连接的两个输入端子，每个对称支路包括恒定电流发生器 和脉冲电流发生器。 提供反馈路径，通过两个环路滤波器端子上可用的电压来控制恒流发电机。 根据本发明，脉冲电流发生器（I7，I8）通过断路切换装置（S1，S2）与各个环路滤波器端子（N1，N2）分离，所述断路切换装置（S1，S2）被控制 通过从相位比较器（2）输出的相位信号（UP，DOWN）。

公开(公告)号：EP0957578A1

公开(公告)日：1999-11-17

申请号：EP98830296.4

申请日：1998-05-15

Applicant: STMicroelectronics S.r.l.

Inventor： De Micheli, Marco ,  Portaluri, Salvatore ,  Bollati, Giacomino ,  Bruccoleri, Melchiorre

IPC: H03H11/04 ,  H03F3/30

CPC classification number: H03F3/3001 ,  H03H11/0472

Abstract: A transconductance control circuit, particularly for a continuous-time filter, comprising a transconductor (4) across which a constant voltage is input; the transconductor is connected to a DAC (7) to set a reference current (I R ); a feedback loop (9, 10, 23, 11) is provided between the output of the transconductor (4) and its input; the particularity of the circuit is the fact that it further comprises means (20, 22, 24) for mirroring the reference current (I R ) set by the DAC (7) which are suitable to mirror the current both to the feedback loop and to at least one cell of a filter which is cascade-connected.

Abstract translation: 一种跨导控制电路，特别是用于连续时间滤波器，包括跨导体（4），输入恒定电压; 跨导器连接到DAC（7）以设置参考电流（IR）; 在跨导体（4）的输出端与其输入端之间提供反馈回路（9,10,23,11） 电路的特殊性是其进一步包括用于镜像由DAC（7）设置的参考电流（IR）的装置（20,22,24），其适于将电流镜像到反馈回路并且到 串联连接的滤波器的至少一个单元。

公开(公告)号：EP0952455A1

公开(公告)日：1999-10-27

申请号：EP98830246.9

申请日：1998-04-23

Applicant: STMicroelectronics S.r.l.

Inventor： Bruccoleri, Melchiorre ,  Ottini, Daniele ,  Demicheli, Marco ,  Bollati, Giacomino

IPC: G01R19/04

CPC classification number: G01R19/22

Abstract: A full-wave rectifier for monitoring the amplitude of a differential analog signal (IN+, IN-) is composed of a differential Track&Hold stage (T&H) controlled by a first differential logic timing signal (TClk+, TClk-), tracking the differential analog input signal (IN+, IN-) during a tracking phase that corresponds to a high logic stage of the first differential timing signal (TClk+, TClk-), producing a differential output signal that is a replica of the input signal and storing it during a successive storing phase that corresponds to a low logic state of the first differential timing signal (TClk+, TClk-); a first differential output amplifier ( ) having inputs coupled to the output of the Track&Hold stage (T&H); a differential bistable circuit (LATCH-ECL), controlled by a second differential logic timing signal (DClk+, DClk-), having inputs coupled to the differential outputs of the first amplifier ( ) and producing a third differential logic control signal (S+, S-); a second multiplexed amplifier (Analog-Amp ), controlled by the third differential control signal (S+, S-), having inputs coupled to the output of the Track&Hold stage (T&H) and outputting a differential analog signal (OUT+, OUT-) of amplitude function of the amplitude of the differential input signal (IN+, IN-); a timing circuit (T C ) receiving at an input a differential logic synchronism signal (Clk+, Clk-) and generating the first differential timing signal (TClk+, TClk-) of said Track&Hold stage (T&H) and the second differential timing signal (DClk+, DClk-) of said bistable circuit (LATCH-ECL).

Abstract translation: 用于监视差分模拟信号（IN +，IN-）的幅度的全波整流器由由第一差分逻辑定时信号（TClk +，TClk-）控制的差分跟踪保持级（T＆H）组成，跟踪差分模拟输入 在对应于第一差分定时信号（TClk +，TClk-）的高逻辑级的跟踪阶段的信号（IN +，IN-）），产生作为输入信号的复制品的差分输出信号并在连续的期间存储 存储相位对应于第一差分定时信号（TClk +，TClk-）的低逻辑状态; 具有耦合到轨道和保持级（T＆amp; H）的输出的输入的第一差分输出放大器（@）; 由第二差分逻辑定时信号（DClk +，DClk-）控制的差分双稳态电路（LATCH-ECL）具有耦合到第一放大器（@）的差分输出的输入，并产生第三差分逻辑控制信号（S + S-）; 由第三差分控制信号（S +，S-）控制的第二多路复用放大器（Analog-Amp @），具有耦合到跟踪和保持级（T＆amp; H）的输出并输出差分模拟信号（OUT +，OUT-） 幅度函数的差分输入信号（IN +，IN-）的幅度; 定时电路（T @ C @）在输入端接收差分逻辑同步信号（Clk +，Clk-）并产生所述跟踪和保持级（T＆amp; H）的第一差分定时信号（TClk +，Tclk-）和第二差分定时信号 （LATCH-ECL）的（DClk +，DClk-）。