公开(公告)号：EP1717817A1

公开(公告)日：2006-11-02

申请号：EP05103557.4

申请日：2005-04-29

Applicant: STMicroelectronics S.r.l.

Inventor： Resta, Claudio ,  Bedeschi, Ferdinando

IPC: G11C16/34 ,  G11C16/02

CPC classification number: G11C13/0004 ,  G11C11/22 ,  G11C11/2275 ,  G11C13/0033 ,  G11C13/0069 ,  G11C16/3431 ,  G11C2013/0083

Abstract: A semiconductor memory device ( 100 ), including a plurality of programmable memory cells ( MC ) each one adapted to be brought into one among at least a first status and a second status, said plurality of memory cells including memory cells intended to store data, and means for accessing ( 115,130,135 ) the memory cells for reading/modifying their status. At least one memory cell ( FMC ) in said plurality is used as detector memory cell, and control means ( 145 ) operatively associated with the at least one detector memory cell are provided, said control means being adapted to establishing a potential loss of the data stored in the memory cells of said plurality based on a detected first status of the at least one detector memory cell.

Abstract translation: 一种半导体存储器件（100），包括多个可编程存储器单元（MC），每个可编程存储器单元适于在至少第一状态和第二状态之间变成一个，所述多个存储器单元包括用于存储数据的存储器单元， 以及用于访问（115,130,135）存储器单元以读取/修改其状态的装置。 所述多个中的至少一个存储单元（FMC）用作检测器存储单元，并且提供与至少一个检测器存储单元可操作地相关联的控制装置（145），所述控制装置用于建立数据的潜在损失 基于所检测到的至少一个检测器存储单元的第一状态存储在所述多个存储单元中。

公开(公告)号：EP1624459A1

公开(公告)日：2006-02-08

申请号：EP04425601.4

申请日：2004-08-03

Applicant: STMicroelectronics S.r.l.

Inventor： Bedeschi, Ferdinando ,  Resta, Claudio

IPC: G11C11/34 ,  H01L27/24

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/009

Abstract: A nonvolatile phase change memory device (1) including a memory array (2) formed by memory cells (3) arranged in rows and columns, word lines (4) connected to first terminals of memory cells (3) arranged on the same row, and bit lines (5) connected to second terminals of memory cells (3) arranged on the same column, a row decoder (6) coupled to the memory array (2) to bias the word lines (4), a column decoder (7) coupled to the memory array (2) to bias the bit lines (5), and a biasing circuit (8) coupled to the row decoder (6) and to the column decoder (7) to supply a first biasing voltage ( V A ) and a second biasing voltage ( V SS ) to the terminals of an addressed memory cell (3), wherein the first biasing voltage ( V A ) is a positive biasing voltage and the second biasing voltage ( V SS ) is a negative biasing voltage.

Abstract translation: 一种非易失性相变存储器件（1），包括由以列和列排列的存储单元（3）形成的存储器阵列（2），连接到布置在同一行上的存储单元（3）的第一端子的字线（4） 和连接到布置在同一列上的存储器单元（3）的第二端子的位线（5），耦合到存储器阵列（2）以偏置字线（4）的行解码器（6），列解码器（7） ）耦合到存储器阵列（2）以偏置位线（5），以及耦合到行解码器（6）和列解码器（7）的偏置电路（8）以提供第一偏置电压（VA） 以及第二偏置电压（V SS）到寻址的存储单元（3）的端子，其中第一偏置电压（VA）是正偏置电压，第二偏置电压（V SS）是负偏置电压。

公开(公告)号：EP1489622A1

公开(公告)日：2004-12-22

申请号：EP03425390.6

申请日：2003-06-16

Applicant: STMicroelectronics S.r.l.

Inventor： Resta, Claudio ,  Bedeschi, Ferdinando ,  Pellizzer, Fabio ,  Casagrande, Giulio

IPC: G11C11/34

CPC classification number: G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/79

Abstract: A memory device (20) of a phase change type, wherein a memory cell (2) has a memory element (3) of calcogenic material switcheable between at least two phases associated with two different states of the memory cell. A write stage (24) is connected to the memory cell and has a capacitive circuit (35) configured to generate a discharge current used as write current having no constant portion and causing the memory cell (2) to change state.

Abstract translation: 一种相变型存储器件（20），其中存储单元（2）具有可在存储单元的两种不同状态相关联的至少两相之间切换的钙质材料的存储元件（3）。 写入级（24）连接到存储单元，并具有电容电路（35），其被配置为产生用作不具有常数部分的写入电流的放电电流，并使存储器单元（2）改变状态。