公开(公告)号：EP2034536A1

公开(公告)日：2009-03-11

申请号：EP07425555.5

申请日：2007-09-07

Applicant: STMicroelectronics S.r.l. ,  Politecnico di Milano

Inventor： Redaelli, Andrea ,  Pellizzer, Fabio ,  Pirovano, Agostino

IPC: H01L45/00

CPC classification number: H01L45/1233 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/126 ,  H01L45/144

Abstract: A phase change memory device (10) having a heater element (2) and memory region (3) of chalcogenic material. The memory region has a phase changing portion (5) in electrical and thermal contact with the heater element and forms a first current path between the heater element and a rest portion (4) of the memory element. The phase changing portion (5) has a dimension correlated to information stored in the memory region and a higher resistivity than the rest portion (4). A parallel current path (11) extends between the heater element (2) and the rest portion (4) of said memory element and has a resistance depending upon the dimension of the phase changing portion (5) and lower than the phase changing portion (5), thus modulating the overall resistance of phase change memory device.

Abstract translation: 具有加热器元件（2）和存储区域（3）的相变材料的相变存储器件（10）。 存储区域具有与加热器元件电接触和热接触的相变部分（5），并且在加热器元件和存储元件的其余部分（4）之间形成第一电流路径。 相位改变部分（5）具有与存储在存储区域中的信息相关的维度，并且比其余部分（4）具有更高的电阻率。 平行电流路径（11）在加热器元件（2）和所述存储元件的其余部分（4）之间延伸，并且具有取决于相变部分（5）的尺寸并且低于相变部分 5），从而调制相变存储器件的整体电阻。

公开(公告)号：EP2015357A1

公开(公告)日：2009-01-14

申请号：EP07425423.6

申请日：2007-07-09

Applicant: STMicroelectronics S.r.l.

Inventor： Pellizzer, Fabio ,  Benvenuti, Augusto ,  Cappelletti, Paolo ,  Bez, Roberto ,  Pirovano, Agostino

IPC: H01L21/8229 ,  H01L27/102 ,  H01L27/24 ,  H01L45/00

CPC classification number: H01L27/1022 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233

Abstract: A process for manufacturing an array of cells in a body (1) of semiconductor material wherein a common conduction region (11) of a first conductivity type and a plurality of shared control regions (12), of a second conductivity type, are formed in the body. The shared control regions (12) extend on the common conduction region (11) and are laterally delimited by insulating regions (32). Then, a grid-like layer (36) is formed on the body (1) to delimit a first plurality of empty regions (38) directly overlying the body and conductive regions of semiconductor material and the first conductivity type (44) are formed by filling the first plurality of empty regions (38), each conductive region forming, together with the common conduction region and an own shared control region (12), a bipolar junction transistor (20).

Abstract translation: 于一体的制造单元的阵列的方法（1）的半导体材料的worin的第一导电类型的公共导电区（11）和一个第二导电类型的共享控制区域（12）的复数，在形成 身体。 共享控制区（12）上的公共导电区（11）延伸，并且尾盘反弹通过绝缘区域（32）分隔。 然后，网格状层（36）形成在所述主体（1）来分隔空区域的第一多个（38）直接覆盖所述主体和半导体材料的导电区域和第一导电类型（44）由形成 填充空区域（38），每个导电区域上形成的第一多个，与普通传导区在一起并且连接到自己的共享控制区域（12），双极结型晶体管（20）。

公开(公告)号：EP1965427A1

公开(公告)日：2008-09-03

申请号：EP07425107.5

申请日：2007-02-28

Applicant: STMicroelectronics S.r.l.

Inventor： Magistretti, Michele ,  Pellizzer, Fabio ,  Benvenuti, Augusto

IPC: H01L27/102

CPC classification number: H01L27/1022 ,  H01L21/76205 ,  H01L21/76224 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

Abstract: A process for manufacturing an array of bipolar transistors, wherein deep field insulation regions (26) of dielectric material are formed in a semiconductor body (21), thereby defining a plurality of active areas (22), insulated from each other and a plurality of bipolar transistors are formed in each active area. In particular, in each active area, a first conduction region (24) is formed at a distance from the surface of the semiconductor body (21); a control region (25) is formed on the first conduction region (24); and, in each control region, at least two second conduction regions (31) and at least one control contact region (36) are formed. The control contact region (36) is interposed between the second conduction regions (31) and at least two surface field insulation regions (29) are thermally grown in each active area (22) between the control contact region (36) and the second conduction regions (31).

Abstract translation: 一种用于制造双极晶体管阵列的方法，其中介电材料的深场绝缘区域（26）形成在半导体本体（21）中，从而限定出彼此绝缘的多个有源区域（22）和多个 在每个有效区域中形成双极晶体管。 特别地，在每个有源区域中，形成与半导体本体（21）的表面相距一定距离的第一导电区域（24）。 在所述第一导电区域（24）上形成控制区域（25）。 并且在每个控制区域中形成至少两个第二导电区域（31）和至少一个控制接触区域（36）。 控制接触区域（36）介于第二导电区域（31）之间，并且至少两个表面场绝缘区域（29）在控制接触区域（36）和第二导电区域（36）之间的每个有源区域（22）中热生长 地区（31）。

公开(公告)号：EP1408549B1

公开(公告)日：2007-03-07

申请号：EP02425604.2

申请日：2002-10-08

Applicant: STMicroelectronics S.r.l. ,  Ovonyx Inc.

Inventor： Pellizzer, Fabio ,  Casagrande, Giulio ,  Gastaldi, Roberto ,  Vendrame, Loris ,  Benvenuti, Augusto ,  Lowrey, Tyler, c/o Ovonyx Inc.

IPC: H01L27/10 ,  H01L29/68 ,  H01L45/00

CPC classification number: H01L29/685 ,  H01L27/101 ,  H01L27/24

公开(公告)号：EP1505656B1

公开(公告)日：2007-01-03

申请号：EP03425536.4

申请日：2003-08-05

Applicant: STMicroelectronics S.r.l.

Inventor： Pellizzer, Fabio ,  Bez, Roberto

IPC: H01L27/24

CPC classification number: H01L27/2472 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

公开(公告)号：EP1408550B1

公开(公告)日：2006-12-27

申请号：EP02425605.9

申请日：2002-10-08

Applicant: STMicroelectronics S.r.l. ,  Ovonyx Inc.

Inventor： Pellizzer, Fabio ,  Casagrande, Giulio ,  Bez, Roberto

IPC: H01L27/10 ,  H01L29/68 ,  H01L45/00

CPC classification number: H01L27/2445 ,  H01L27/101 ,  H01L27/2463 ,  H01L29/685 ,  H01L45/06 ,  H01L45/1233

公开(公告)号：EP1710807A1

公开(公告)日：2006-10-11

申请号：EP05102811.6

申请日：2005-04-08

Applicant: STMicroelectronics S.r.l.

Inventor： Pellizzer, Fabio ,  Varesi, Enrico ,  Pirovano, Agostino

IPC: G11C16/02 ,  H01L45/00

CPC classification number: H01L45/06 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

Abstract: A phase change memory cell includes a phase change region of a phase change material, a heating element (30) of a resistive material, arranged in contact with the phase change region (33') and a memory element (35) formed in said phase change region at a contact area with the heating element (30). The contact area is in the form of a frame that has a width of sublithographic extent (S) and, preferably, a sublithographic maximum external dimension. The heating element (30) includes a hollow elongated portion which is arranged in contact with the phase change region (33').

Abstract translation: 相变存储单元包括相变材料的相变区域，与相变区域（33'）接触地布置的电阻材料的加热元件（30）和形成在所述相位中的存储元件（35） 在与加热元件（30）的接触区域处的变化区域。 接触区域为具有亚光刻范围（S）的宽度的框架的形式，并且优选为亚光刻最大外部尺寸。 加热元件（30）包括与相变区域（33'）接触地布置的中空细长部分。

公开(公告)号：EP1489622A1

公开(公告)日：2004-12-22

申请号：EP03425390.6

申请日：2003-06-16

Applicant: STMicroelectronics S.r.l.

Inventor： Resta, Claudio ,  Bedeschi, Ferdinando ,  Pellizzer, Fabio ,  Casagrande, Giulio

IPC: G11C11/34

CPC classification number: G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/79

Abstract: A memory device (20) of a phase change type, wherein a memory cell (2) has a memory element (3) of calcogenic material switcheable between at least two phases associated with two different states of the memory cell. A write stage (24) is connected to the memory cell and has a capacitive circuit (35) configured to generate a discharge current used as write current having no constant portion and causing the memory cell (2) to change state.

Abstract translation: 一种相变型存储器件（20），其中存储单元（2）具有可在存储单元的两种不同状态相关联的至少两相之间切换的钙质材料的存储元件（3）。 写入级（24）连接到存储单元，并具有电容电路（35），其被配置为产生用作不具有常数部分的写入电流的放电电流，并使存储器单元（2）改变状态。

公开(公告)号：EP1475840A1

公开(公告)日：2004-11-10

申请号：EP03425292.4

申请日：2003-05-07

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Pellizzer, Fabio ,  Bez, Roberto

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126

Abstract: A process for manufacturing a memory device having selector bipolar transistors (25) for storage elements (65), includes the steps of: in a semiconductor body (20), forming at least a selector transistor (25), having at least an embedded conductive region (26), and forming at least a storage element (65), stacked on and electrically connected to the selector transistor (25); moreover, the step of forming at least a selector transistor (25) includes forming at least a raised conductive region (35, 36) located on and electrically connected to the embedded conductive region (26).

Abstract translation: 一种用于制造具有存储元件选择双极型晶体管（25）（65）的存储器器件的方法包括以下步骤：在半导体本体（20），形成至少上嵌入的导电至少具有选择晶体管（25） 区域（26），和至少形成存储元件（65），堆叠​​在并且电连接到选择晶体管（25）; 更完了，形成至少一个选择晶体管（25）的步骤包括形成至少位于并电连接到嵌入的导电区域（26）的凸起的导电区域（35，36）。

公开(公告)号：EP1318552A1

公开(公告)日：2003-06-11

申请号：EP01128461.9

申请日：2001-12-05

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Bez, Roberto ,  Pellizzer, Fabio ,  Riva, Caterina ,  Zonca, Romina

IPC: H01L45/00 ,  G11C11/34 ,  H01L27/24

CPC classification number: G11C13/0004 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691 ,  Y10S438/947

Abstract: A contact structure (30) in an electronic semiconductor device, including a first conducting region (31) having a first thin portion with a first sublithographic dimension in a first direction; a second conducting region (32) having a second thin portion (32a) with a second sublithographic dimension in a second direction transverse to said first direction; the first and second conducting regions being in direct electrical contact at the first and second thin portions and defining a contact area (33) having a sublithografic extension, lower than 100 nm, preferably about 20 nm. The thin sublithographic portions are obtained using deposition instead of lithography: the first thin portion is deposed on a wall of an opening in a first dielectric layer (34); the second thin portion is obtained by deposing a sacrificial region on vertical wall of a first delimitation layer, deposing a second delimitation layer on the free side of the sacrificial region, removing the sacrificial region to form a sublithographic hard mask opening that is used to etch a mold opening (40) in a mold layer (38) and filling the mold opening.

Abstract translation: 在半导体电子器件，其包括具有在第一方向上的第一亚光刻尺寸的第一薄壁部的第一导电区域（31）的接触结构（30）; 具有在第二方向上横向于所述第一方向的第二亚光刻尺寸的第二薄壁部（32A）的第二导电区（32）; 第一和第二导电区域在所述第一和第二薄膜部分直接电接触和限定具有sublithografic延伸的接触区域（33），低于100nm，优选约20nm。薄亚光刻的部分获得使用沉积代替 光刻的：所述第一薄壁部的设置于在第一电介质层（34）中的开口的壁; 所述第二薄壁部是通过在第一划界层的垂直壁罢免牺牲区域，在所述牺牲区域的自由侧罢免第二划界层，去除牺牲区域以形成亚光刻硬掩模开口获得并用于蚀刻 在模制层（38）和填充所述模具开口的模具开口（40）。