公开(公告)号：EP0969507A1

公开(公告)日：2000-01-05

申请号：EP98830390.5

申请日：1998-06-30

Applicant: STMicroelectronics S.r.l.

Inventor： Pio, Federico

IPC: H01L21/8247 ,  H01L27/115 ,  H01L21/336

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/66825

Abstract: An EEPROM memory cell (1,30) integrated in a semiconductor substrate (2) comprises a floating gate MOS transistor (3,31) having a source region (4,33), a drain region (5,34), and a gate region (6,35) projecting from the substrate (2) and is isolated from the substrate (2) by an oxide layer (7,36') including a thinner tunnel portion (8,36) and heavily doped regions (9,37) formed under said tunnel portion (8,36) and extending to beneath the drain region (5,34), and a selection transistor (10,32) having a source region (38), a drain region (39) and a gate region (40), wherein said source region (4,33) is heavily doped and formed simultaneously with said heavily doped regions (9,37).

Abstract translation: 集成在半导体衬底（2）中的EEPROM存储单元（1,30）包括具有源极区（4,33），漏极区（5,34）和栅极（3）的浮栅MOS晶体管（3,31） 从衬底（2）突出并且通过包括较薄的隧道部分（8,36）和重掺杂区域（9,37）的氧化物层（7,36'）与衬底（2）隔离的区域（6,35） ）形成在所述隧道部分（8,36）下方并延伸到漏极区（5,34）下方，以及选择晶体管（10,32），其具有源极区（38），漏极区（39）和栅极 区域（40），其中所述源极区域（4,33）被重掺杂并与所述重掺杂区域（9,37）同时形成。

公开(公告)号：EP0654791B1

公开(公告)日：1999-07-28

申请号：EP93830464.9

申请日：1993-11-24

Applicant: STMicroelectronics S.r.l.

Inventor： Baldi, Livio ,  Pio, Federico

IPC: G11C16/06

CPC classification number: G11C16/30 ,  G11C16/12

公开(公告)号：EP0928030A1

公开(公告)日：1999-07-07

申请号：EP97830744.5

申请日：1997-12-31

Applicant: STMicroelectronics S.r.l.

Inventor： Pio, Federico ,  Riva, Carlo

IPC: H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L21/336 ,  H01L27/088

CPC classification number: H01L29/66575 ,  H01L21/823418 ,  H01L21/823443 ,  H01L27/088 ,  H01L27/105 ,  H01L29/41725 ,  H01L29/456 ,  H01L29/7833

Abstract: An HV transistor (2) integrated in a semiconductor substrate (1) with a first type of conductivity, comprising a gate region (12) included between corresponding drain (16) and source (17) regions, and being of the type wherein at least said drain region (16) is lightly doped with a second type of conductivity. The drain region (16) comprises a contact region (7) with the second type of conductivity but being more heavily doped, from which a contact pad (21) stands proud.

Abstract translation: 集成在具有第一类型导电性的半导体衬底（1）中的HV晶体管（2）包括在相应的漏极（16）和源极（17）区域之间包括的栅极区域（12），并且是至少 所述漏极区域（16）被轻掺杂第二类导电性。 漏极区域（16）包括具有第二类导电性但是更重掺杂的接触区域（7），接触垫（21）从该接触区域引出。

公开(公告)号：EP1715491A3

公开(公告)日：2006-11-02

申请号：EP06012616.6

申请日：1999-04-21

Applicant: STMicroelectronics S.r.l.

Inventor： Gomiero, Enrico ,  Pio, Federico ,  Zuliani, Paola

IPC: G11C16/04

CPC classification number: G11C16/12 ,  G11C16/0433 ,  G11C16/30

Abstract: This invention relates to a method of adjusting the erase/program voltage in semiconductor non-volatile memories. The memories are formed of at least one matrix of memory cells having a floating gate, a control gate, and drain and source terminals, and are organised by the byte in rows (WL) and columns (BL), each byte comprising a group of cells having respective control gates connected in parallel with one another to a common control line (CG) through a selection element of the byte switch type, and each cell being connected to a respective control column (BL) through a selection element of the bit switch type. Advantageously, a double adjustment is provided for the program voltage of the memory cells, whereby the program voltage during the erasing phase can be higher in modulo than the program voltage during the writing phase. This is achieved by forming the bit switch element (20) inside a well (13) and the byte switch element (21) directly in the substrate.

公开(公告)号：EP1339069B1

公开(公告)日：2004-07-07

申请号：EP02425084.7

申请日：2002-02-20

Applicant: STMicroelectronics S.r.l.

Inventor： Pio, Federico

IPC: G11C16/08 ,  G11C16/16

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C16/16

公开(公告)号：EP1339069A1

公开(公告)日：2003-08-27

申请号：EP02425084.7

申请日：2002-02-20

Applicant: STMicroelectronics S.r.l.

Inventor： Pio, Federico

IPC: G11C16/08 ,  G11C16/16

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C16/16

Abstract: A word line selector for selecting word lines ( WL1 - WLm ) of an array ( 101 ) of semiconductor memory cells ( MC ) formed in a doped semiconductor region ( 103 ) of a semiconductor substrate ( 107 ) comprises a plurality of word line drivers ( 3011 , 3012 ) responsive to word line selection signals ( WLSA1 , WLSa2 ). Each word line driver is associated with a respective word line for driving the word line to prescribed word line electric potentials, depending on an operation to be conducted on the array of memory cells, in accordance with the word line selection signal. A plurality of distinct doped semiconductor well structures ( 115a - 115p ) is provided in the semiconductor substrate. Each doped semiconductor well structure accommodates a respective group ( 113a - 113p ) of at least one word line driver associated with a respective group ( WL1 - WLh , WLk - WLm ) of at least one word line. The different doped semiconductor well structures can thus be biased independently of each other to respective semiconductor well bias potentials, so that the word line potentials of word lines of different groups need not be correlated.

Abstract translation: 字线选择器，用于选择字线（WL1 - WLM）在半导体衬底（107）的掺杂的半导体区域（103）形成的半导体存储单元（MC）包括字线驱动器的多个阵列（101）的（ 3011.3012），响应于字线选择信号（WLSA1，WLSa2）。 每个字线驱动器与用于驱动所述字线到规定的字线的电势，这取决于1年操作的存储器单元的阵列上进行，在与该字线选择信号，根据相应的字线相关联。 不同掺杂半导体阱结构的多个（115A - 115P）在半导体基板上设置。 每个掺杂的半导体阱结构容纳的相应组（113A - 113P），其具有至少一个字线中的相应组（WL1-WLH，WLK-WLm的）相关联的至少一个字线驱动器的。 不同的掺杂半导体阱结构可以偏置，这样indépendamment彼此以各自的半导体阱偏置电位，所以不同组的字线阙LA字线的电位不必相关。

公开(公告)号：EP0953984B1

公开(公告)日：2003-07-02

申请号：EP98830265.9

申请日：1998-04-30

Applicant: STMicroelectronics S.r.l.

Inventor： Pio, Federico

IPC: G11C16/00 ,  G11C16/06 ,  G11C5/14

CPC classification number: G11C16/105 ,  G11C5/143 ,  G11C16/102

公开(公告)号：EP0730277B1

公开(公告)日：2002-11-13

申请号：EP95830064.2

申请日：1995-02-28

Applicant: STMicroelectronics S.r.l.

Inventor： Pio, Federico ,  Paruzzi, Paola

IPC: G11C16/00 ,  H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524

公开(公告)号：EP1233421A1

公开(公告)日：2002-08-21

申请号：EP01830110.1

申请日：2001-02-19

Applicant: STMicroelectronics S.r.l.

Inventor： Pio, Federico

IPC: G11C16/34

CPC classification number: G11C16/3418

Abstract: Method for refreshing data stored in an electrically erasable and programmable non-volatile semiconductor memory comprising at least one two-dimensional array (1) of memory cells (MC) containing a plurality of individually erasable and programmable memory pages (R). Each time a request to modify a content of a memory page is received by the memory, the method provides for modifying (201;502;602) the content of said memory page and submitting a portion (S1-SZ;R) of the two-dimensional array to a refresh procedure (202-208;501,503-509;601,603-612). The refresh procedure comprises detecting (203;505;606) memory cells of that memory portion that have partially lost a respective datum stored therein and reprogramming the datum in the detected memory cells.

Abstract translation: 对于存储在电可擦除和可编程的非易失性半导体存储器，包括存储单元（MC）包含单独可擦除和可编程存储器页（R）的多个的至少一个二维阵列（1）刷新数据的方法。 每个时间的请求来修改存储器页的内容由存储器接收，该方法提供了用于修饰（201; 502; 602）所述存储器页的内容和提交的部分（S1-SZ; R）两者的 维阵列的刷新程序（202-208; 501.503至509; 601.603到612）。 （203; 505; 606）的刷新程序包括：检测存储器部分中的存储单元并thathave部分失去一个respectivement日期所存和重新编程在检测到的存储器单元的时间。

公开(公告)号：EP1006568A1

公开(公告)日：2000-06-07

申请号：EP98830722.9

申请日：1998-12-02

Applicant: STMicroelectronics S.r.l.

Inventor： Pio, Federico

IPC: H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/31116 ,  H01L21/32136

Abstract: During critical plasma etching steps, the wafer's surface is illuminated with electromagnetic radiation in the visible and/or in UV spectrum of energy and power density sufficient to enhance the reverse current through protective junctions that are commonly realized for providing electrical discharge paths for electrical charges picked up by exposed conductive parts to limit the level of induced voltages to values compatible with the preservation of the integrity of functional dielectric layers coupled to the exposed conductors parts and to the semiconductor substrate or to another conductive part.

Abstract translation: 在临界等离子体蚀刻步骤期间，晶片的表面以能量和/或紫外光谱中的电磁辐射被照射，能量和功率密度足以增强通过保护结的反向电流，这通常被实现为提供用于选择的电荷的放电路径 通过暴露的导电部件将感应电压的电平限制为与保持耦合到暴露的导体部分和半导体衬底或另一个导电部分的功能电介质层的完整性兼容的值。