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    High-voltage transistor structure for handling high-voltages in CMOS integrated circuits
    2.
    发明公开
    High-voltage transistor structure for handling high-voltages in CMOS integrated circuits 审中-公开
    在CMOS处理高电压的高电压的晶体管结构的集成电路

    公开(公告)号：EP1001466A1

    公开(公告)日：2000-05-17

    申请号：EP98830675.9

    申请日：1998-11-10

    Applicant: STMicroelectronics S.r.l.

    Inventor： Riva, Carlo ,  Ghezzi, Paolo ,  Maurelli, Alfonso

    IPC: H01L27/105 ,  H01L27/088 ,  H01L21/8234

    CPC classification number: H01L27/088 ,  H01L21/823462 ,  H01L27/105

    Abstract: High-voltage transistor structure, particularly for handling programming and/or programming and erasing voltages for electrically programmable and/or electrically programmable and erasable non-volatile memory cells which are integrated together with the high-voltage transistor and a low-voltage logic circuitry in a same semiconductor chip, the logic circuitry comprising first conductivity type channel transistors and second conductivity type channel transistors respectively formed inside second conductivity type wells (2) and first conductivity type wells (3), the first and second conductivity type wells (2,3) formed in a common substrate (1) of the first conductivity type which forms a common substrate of the semiconductor chip, the high-voltage transistor comprising an insulated gate electrode (10) and source and drain electrodes (9) at the sides of the insulated gate electrode (10). The insulated gate electrode (10) is insulated from the underlying common substrate (1) of the first conductivity type by a portion of a thick field oxide (4), and the source and drain electrodes (9) are doped regions of a second conductivity type formed directly in said common substrate (1).

    Abstract translation: 高压晶体管结构，特别是用于处理编程和/或编程和擦除电压为电可编程和/或电可编程和可擦除的非易失性存储器，其与所述高电压晶体管和低电压逻辑电路集成在一起的单元 相同的半导体芯片，所述逻辑电路包括第一导电类型沟道的晶体管及第二导电类型沟道的晶体管内第二导电型阱分别形成（2）和第一导电类型的井（3）中，第一及第二导电型的井（2.3 衬底），形成在一个共同的（1），其形成在半导体芯片的一个公共基底上的第一导电类型的，高电压晶体管绝缘栅电极（10）和源极的包括电极和漏电极（9）的侧面 绝缘栅电极（10）。 绝缘栅电极（10）被从底层共同基底绝缘（1）由一个厚的场氧化物的部分的第一导电类型的（4），以及源电极和漏电极（9）掺杂一第二导电性的区域 直接在型形成在所述共用基板（1）。

    A method of producing MOSFET transistors by means of tilted implants
    3.
    发明授权
    A method of producing MOSFET transistors by means of tilted implants 失效
    一种用于通过倾斜注入的手段制备MOSFET晶体管的方法

    公开(公告)号：EP0874389B1

    公开(公告)日：2007-08-01

    申请号：EP97830182.8

    申请日：1997-04-21

    Applicant: STMicroelectronics S.r.l.

    Inventor： Fratin, Lorenzo ,  Riva, Carlo

    IPC: H01L21/265 ,  H01L21/28 ,  H01L29/423

    CPC classification number: H01L29/0847 ,  H01L21/26586 ,  H01L21/28123 ,  H01L29/4238

    Abstract: The method described provides for the following steps: delimiting active areas (81) on a substrate, forming gate electrodes (82, 83, 88) insulated from the substrate on the active areas, and subjecting the front surface of the substrate to several implantation steps with doping ion beams to form source and drain regions with the use of the gate electrodes as masks. The direction of the implantation beam is defined by an angle of inclination to the front surface and by an orientation (45 DEG , 135 DEG , 225 DEG , 315 DEG ) to a reference line (80) on the front surface. To avoid performing numerous implantation steps without foregoing channels of uniform and constant length (L''), the widths of the gate electrode strips (82, 83, 88) are determined at the design stage in dependence on the orientation of the strips to the reference line (80) and on the orientation of the directions of the implant beams.

    Process for forming an integrated circuit comprising non-volatile memory cells and side transistors and corresponding IC
    4.
    发明授权
    Process for forming an integrated circuit comprising non-volatile memory cells and side transistors and corresponding IC 失效
    生产含有非易失性存储单元和外围晶体管的电路的方法，和相应的集成电路

    公开(公告)号：EP0751559B1

    公开(公告)日：2002-11-27

    申请号：EP95830281.2

    申请日：1995-06-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Clementi, Cesare ,  Ghidini, Gabriella ,  Riva, Carlo

    IPC: H01L21/8247 ,  H01L27/115

    CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546

    Abstract: A process for forming an integrated circuit calls for the provision of at least one matrix of non-volatile memory cells (1) having an intermediate dielectric multilayer including at least a lower dielectric material layer (8) and an upper silicon oxide layer (9) and the simultaneous provision in zones peripheral to the matrix of at least one first transistor type (2) having gate dielectric of a first thickness. After formation of the floating gate with a gate oxide layer (4) and a polycrystalline silicon layer (5) and the formation of the lower dielectric material layer (8), the process in accordance with the present invention calls for: removal of said layers from the peripheral zones (R2) of the matrix; deposition of said upper silicon oxide layer (9) over the memory cells (1),and over the substrate (3) in the areas (R2) of the peripheral transistors (2); and formation of a first silicon oxide layer (10) at least in the areas (R2) of the peripheral transistors (2). To provide additionally a second transistor type having gate dielectric of a second thickness, indicatively thinner than said first thickness, successive steps are added in accordance with the present invention.

    A method of producing MOSFET transistors by means of tilted implants
    6.
    发明公开
    A method of producing MOSFET transistors by means of tilted implants 失效
    Ein Verfahren zur Herstellung von MOSFET-Transistoren mittels geneigten Implantierungen

    公开(公告)号：EP0874389A1

    公开(公告)日：1998-10-28

    申请号：EP97830182.8

    申请日：1997-04-21

    Applicant: STMicroelectronics S.r.l.

    Inventor： Fratin, Lorenzo ,  Riva, Carlo

    IPC: H01L21/265 ,  H01L21/28 ,  H01L29/423

    CPC classification number: H01L29/0847 ,  H01L21/26586 ,  H01L21/28123 ,  H01L29/4238

    Abstract: The method described provides for the following steps: delimiting active areas (81) on a substrate, forming gate electrodes (82, 83, 88) insulated from the substrate on the active areas, and subjecting the front surface of the substrate to several implantation steps with doping ion beams to form source and drain regions with the use of the gate electrodes as masks. The direction of the implantation beam is defined by an angle of inclination to the front surface and by an orientation (45°, 135°, 225°, 315°) to a reference line (80) on the front surface. To avoid performing numerous implantation steps without foregoing channels of uniform and constant length (L''), the widths of the gate electrode strips (82, 83, 88) are determined at the design stage in dependence on the orientation of the strips to the reference line (80) and on the orientation of the directions of the implant beams.

    Abstract translation: 所描述的方法提供了以下步骤：限定衬底上的有源区域（81），形成与有源区域上的衬底绝缘的栅电极（82,83,88），并对衬底的前表面进行若干注入步骤 使用掺杂离子束形成源区和漏区，使用栅电极作为掩模。 注入光束的方向由前表面的倾斜角以及正面（45°，135°，225°，315°）到前表面上的参考线（80）的方向限定。 为了避免执行大量的注入步骤而没有前后通道的均匀和恒定的长度（L“），栅极电极条（82,83,88）的宽度根据条带的取向在设计阶段确定 参考线（80）和植入物束的方向的取向。

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