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    Memory device having error detection and correction function, and methods for writing and erasing the memory device
    4.
    发明授权
    Memory device having error detection and correction function, and methods for writing and erasing the memory device 失效
    与所述存储器装置的检错和纠错和用于写入程序和擦除存储器装置

    公开(公告)号：EP0704854B1

    公开(公告)日：1999-12-01

    申请号：EP94830471.2

    申请日：1994-09-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Baldi, Livio

    IPC: G11C29/00 ,  G06F11/10

    CPC classification number: G06F11/1072 ,  G06F11/1064 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C29/00

    Abstract: The present invention relates to a memory device and specifically the multilevel type with error check and correction function and having a data input (DI), a data output (DO) and an address input (AI) and being of the type comprising first memory means (DM) designed to be accessed by means of address for containing user data, second memory means (EM) for containing error data concerning said user data, a control logic (CL) designed to receive in the writing phase from said address input (AI) and said data input (DI) a writing address and user data respectively and to generate error data and to write said data in said first means (DM) and second means (EM) respectively and designed to receive in the reading phase from said address input (AI) a reading address and extract corresponding user data and error data and combine them to correct any errors and supply them to said data output (DO) and characterised in that said second means (EM) are the type designed to be accessed by means of content and said content for access corresponding to addresses of said first means (DM).

    Method for manufacturing differential isolation structures in a semiconductor electronic device and corresponding structure
    6.
    发明公开
    Method for manufacturing differential isolation structures in a semiconductor electronic device and corresponding structure 有权
    一种用于在半导体器件和相应的结构，生产不同的隔离结构的工艺

    公开(公告)号：EP1496548A1

    公开(公告)日：2005-01-12

    申请号：EP03425459.9

    申请日：2003-07-11

    Applicant: STMicroelectronics S.r.l.

    Inventor： Brazzelli, Daniela ,  Baldi, Livio ,  Servalli, Giorgio

    IPC: H01L21/762

    CPC classification number: H01L21/76229

    Abstract: This invention relates to a method for manufacturing isolation structures with different depths in a monolithically integrated semiconductor electronic device. The inventive method comprises a first step of defining active areas on a semiconductor material substrate, a second step of forming isolation structures by realising trenches in said substrate and then filling them with field oxide, a third step of defining lithographically at least a first device area, and a fourth step of reducing the vertical height of the substrate and of the field oxide of said first device area.

    Abstract translation: 本发明涉及一种用于制造具有不同深度的隔离结构中单片集成半导体电子器件的方法。 本发明方法包括的定义上的半导体材料基板的有源区域的第一步骤中，形成在上述基片由真实伊辛沟槽隔离结构，然后与场氧化物，的限定光刻至少第一器件区域的第三步骤填充它们的第二步骤 ，并减少基板和所述第一器件区的场氧化物的垂直高度的第四步骤。

    Non-volatile memory cell and manufacturing process
    7.
    发明公开
    Non-volatile memory cell and manufacturing process 审中-公开
    Festwertspeicherzelle und Herstellungsverfahren

    公开(公告)号：EP1435657A1

    公开(公告)日：2004-07-07

    申请号：EP02425805.5

    申请日：2002-12-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pavan, Alessia ,  Clementi, Cesare ,  Baldi, Livio

    IPC: H01L21/8247 ,  H01L27/115

    CPC classification number: H01L27/11521 ,  H01L27/115

    Abstract: A non-volatile memory cell (1) is described, being integrated on a semiconductor substrate (2) and comprising:

    a floating gate transistor including a source region (S) and a drain region (G), a gate region projecting from the substrate (2) and comprised between the source and drain regions (S, D), the gate region having a predetermined length (L) and width (W) and comprising a first floating gate region (FG) and a control gate region (CG),
    in which the floating gate region (FG) is insulated laterally, along the width (W) direction, by a dielectric layer (9) with low dielectric constant value (K).
    A process for manufacturing non-volatile memory cells (1) on a semiconductor substrate (2) is also described, comprising the following steps:

    form active areas in the semiconductor substrate (2) bounded by an insulating layer (FOX),
    deposit a first conductor material layer (5) on active areas,
    define through a standard photolithographic technique a plurality of floating gate regions (FG),
    form a dielectric layer (9) with low dielectric constant value (K) on the floating gate regions (FG).

    Abstract translation: 描述了集成在半导体衬底（2）上的非易失性存储器单元（1），包括：包括源区（S）和漏区（G）的浮栅晶体管，从衬底 （2）并且包括在源极和漏极区域（S，D）之间，栅极区域具有预定长度（L）和宽度（W），并且包括第一浮动栅极区域（FG）和控制栅极区域（CG） ，其中浮动栅极区域（FG）沿着宽度（W）方向由具有低介电常数值（K）的电介质层（9）侧向绝缘。 还描述了一种用于在半导体衬底（2）上制造非易失性存储单元（1）的工艺，包括以下步骤：在由绝缘层（FOX）限定的半导体衬底（2）中形成有源区， 在有源区域上沉积第一导体材料层（5），通过标准光刻技术限定多个浮动栅极区域（FG），在浮动栅极区域上形成具有低介电常数值（K）的介电层（9） （FG）。

    Method for forming structures self-aligned with each other on a semiconductor substrate
    10.
    发明公开
    Method for forming structures self-aligned with each other on a semiconductor substrate 审中-公开
    西班牙语西班牙语西班牙语西班牙语

    公开(公告)号：EP1435647A1

    公开(公告)日：2004-07-07

    申请号：EP02425806.3

    申请日：2002-12-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Baldi, Livio ,  Clementi, Cesare ,  Pavan, Alessia

    IPC: H01L21/331 ,  H01L21/60

    CPC classification number: H01L29/66272

    Abstract: A method for forming structures self-aligned with each other on a semiconductor substrate (1), comprising the following steps:

    forming, on the semiconductor substrate (1), first regions (3,12) of a first material projecting from the semiconductor substrate (1);
    forming, over the whole of the semiconductor substrate (1), a protective layer (7,16) of a second material selective with respect to the first material;
    removing the protective layer (7,16) to expose said first regions (3,12) through a planarizing step;
    etching said first regions (3,12) to expose said semiconductor substrate (1), and forming second regions (7a,16a) projecting from the substrate (1) of said protective layer.

    Advantageously, spacers are formed on the sidewalls of the first regions.

    Abstract translation: 一种形成在半导体衬底（1）上彼此自对准的结构的方法，包括以下步骤：在半导体衬底（1）上形成从半导体衬底（1）突出的第一材料的第一区域（3,12） （1）; 在整个半导体衬底（1）上形成相对于第一材料选择性的第二材料的保护层（7,16）; 去除所述保护层（7,16）以通过平坦化步骤暴露所述第一区域（3,12）; 蚀刻所述第一区域（3,12）以暴露所述半导体衬底（1），以及形成从所述保护层的衬底（1）突出的第二区域（7a，16a）。 有利地，间隔物形成在第一区域的侧壁上。

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