公开(公告)号：US10790230B2

公开(公告)日：2020-09-29

申请号：US16257171

申请日：2019-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae Song ,  Seunggeol Nam ,  Yeonchoo Cho ,  Seongjun Park ,  Hyeonjin Shin ,  Jaeho Lee

IPC: H01L23/48 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer.

公开(公告)号：US20200035602A1

公开(公告)日：2020-01-30

申请号：US16238208

申请日：2019-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunggeol Nam ,  Hyeonjin Shin ,  Keunwook Shin ,  Changhyun Kim ,  Kyung-Eun Byun ,  Hyunjae Song ,  Eunkyu Lee ,  Changseok Lee ,  Alum Jung ,  Yeonchoo Cho

IPC: H01L23/532 ,  H01L23/528 ,  H01L23/522

Abstract: An interconnect structure and an electronic device including the interconnect structure are disclosed. The interconnect structure may include a metal interconnect having a bottom surface and two opposite side surfaces surrounded by a dielectric layer, a graphene layer on the metal interconnect, and a metal bonding layer providing interface adhesion between the metal interconnect and the graphene layer. The metal bonding layer includes a metal material.

公开(公告)号：US20190157211A1

公开(公告)日：2019-05-23

申请号：US16257171

申请日：2019-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae SONG ,  Seunggeol Nam ,  Yeonchoo Cho ,  Seongjun Park ,  Hyeonjin Shin ,  Jaeho Lee

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53209 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/5226

Abstract: Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer.

公开(公告)号：US09721943B2

公开(公告)日：2017-08-01

申请号：US15052290

申请日：2016-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changseok Lee ,  Keunwook Shin ,  Hyeonjin Shin ,  Seongjun Park ,  Hyunjae Song ,  Hyangsook Lee ,  Yeonchoo Cho

IPC: H01L23/528 ,  H01L27/06

CPC classification number: H01L27/0629 ,  H01L23/53271 ,  H01L27/101 ,  H01L27/228

Abstract: A wiring structure may include at least two conductive material layers and a two-dimensional layered material layer in an interface between the at least two conductive material layers. The two-dimensional layered material layer may include a grain expander layer which causes grain size of a conductive material layer which is on the two-dimensional layered material layer to be increased. Increased grain size may result in resistance of the second conductive material layer to be reduced. As a result, the total resistance of the wiring structure may be reduced. The two-dimensional layered material layer may contribute to reducing a total thickness of the wiring structure. Thus, a low-resistance and high-performance wiring structure without an increase in a thickness thereof may be implemented.

公开(公告)号：US12255244B2

公开(公告)日：2025-03-18

申请号：US18171502

申请日：2023-02-20

Applicant: Samsung Electronics Co., Ltd. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Inventor： Minhyun Lee ,  Minsu Seol ,  Ho Won Jang ,  Yeonchoo Cho ,  Hyeonjin Shin

IPC: H01L29/423 ,  H01L29/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66

Abstract: Provided is a field effect transistor including a gate insulating layer having a two-dimensional material. The field effect transistor may include a first channel layer; a second channel layer disposed on the first channel layer; a gate insulating layer disposed on the second channel layer; a gate electrode disposed on the gate insulating layer; a first electrode electrically connected to the first channel layer; and a second electrode electrically connected to the second channel layer. Here, the gate insulating layer may include an insulative, high-k, two-dimensional material.

公开(公告)号：US12103850B2

公开(公告)日：2024-10-01

申请号：US17060893

申请日：2020-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Van Luan Nguyen ,  Keunwook Shin ,  Hyeonjin Shin ,  Changhyun Kim ,  Changseok Lee ,  Yeonchoo Cho

IPC: B32B9/00 ,  C01B32/186

CPC classification number: C01B32/186 ,  Y10T428/30

Abstract: A method of forming graphene includes: preparing a substrate in a reaction chamber; performing a first growth process of growing a plurality of graphene aggregates apart from each other on the substrate at a first growth rate by using a reaction gas including a carbon source; and performing a second growth process of forming a graphene layer by growing the plurality of graphene aggregates at a second growth rate slower than the first growth rate by using the reaction gas including the carbon source.

公开(公告)号：US12027589B2

公开(公告)日：2024-07-02

申请号：US17087968

申请日：2020-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook Shin ,  Hyeonjin Shin ,  Yeonchoo Cho ,  Seunggeol Nam ,  Seongjun Park ,  Yunseong Lee

IPC: H01L29/16 ,  C01B32/186 ,  H01L21/02

CPC classification number: H01L29/1606 ,  C01B32/186 ,  H01L21/02384 ,  H01L21/02389 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/02398 ,  H01L21/02488 ,  H01L21/02527 ,  H01L21/0262

Abstract: Provided is a semiconductor device including graphene. The semiconductor device includes: a substrate including an insulator and a semiconductor; and a graphene layer configured to directly grow only on a surface of the semiconductor, wherein the semiconductor includes at least one of a group IV material and a group III-V compound.

公开(公告)号：US11985910B2

公开(公告)日：2024-05-14

申请号：US17836435

申请日：2022-06-09

Applicant: Samsung Electronics Co., Ltd. ,  President and Fellows Of Harvard College

Inventor： Minhyun Lee ,  Dovran Amanov ,  Renjing Xu ,  Houk Jang ,  Haeryong Kim ,  Hyeonjin Shin ,  Yeonchoo Cho ,  Donhee Ham

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/826 ,  H10B63/80 ,  H10N70/24 ,  H10N70/8416

Abstract: Provided are memristors and neuromorphic devices including the memristors. A memristor includes a lower electrode and an upper electrode that are apart from each other and first and second two-dimensional material layers that are arranged between the lower electrode and the upper electrode and stacked without a chemical bond therebetween.

公开(公告)号：US11626502B2

公开(公告)日：2023-04-11

申请号：US17398363

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjin Shin ,  Sangwon Kim ,  Kyung-Eun Byun ,  Hyunjae Song ,  Keunwook Shin ,  Eunkyu Lee ,  Changseok Lee ,  Yeonchoo Cho ,  Taejin Choi

IPC: H01L29/45 ,  H01L29/40 ,  H01L29/15 ,  H01L27/108

Abstract: An interconnect structure for reducing a contact resistance, an electronic device including the same, and a method of manufacturing the interconnect structure are provided. The interconnect structure includes a semiconductor layer including a first region having a doping concentration greater than a doping concentration of a peripheral region of the semiconductor layer, a metal layer facing the semiconductor layer, a graphene layer between the semiconductor layer and the metal layer, and a conductive metal oxide layer between the graphene layer and the semiconductor and covering the first region.

公开(公告)号：US11532709B2

公开(公告)日：2022-12-20

申请号：US17203010

申请日：2021-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun Lee ,  Minsu Seol ,  Yeonchoo Cho ,  Hyeonjin Shin

IPC: H01L29/10 ,  H01L29/24 ,  H01L29/423

Abstract: A field effect transistor includes a substrate, a source electrode and a drain electrode on the substrate and apart from each other in a first direction, a plurality of channel layers, a gate insulating film surrounding each of the plurality of channel layers, and a gate electrode surrounding the gate insulating film. Each of the plurality of channel layers has ends contacting the source electrode and the drain electrode. The plurality of channel layers are spaced apart from each other in a second direction away from the substrate. The plurality of channel layers include a 2D semiconductor material.