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公开(公告)号：AU2066383A
公开(公告)日：1984-05-03
申请号：AU2066383
申请日：1983-10-27
Applicant: TANDEM COMPUTERS INC
Inventor： ALLEN JAMES CONARD , BARTLETT WENDY BOHLE , JOHNSON HOKE STEPHENS , FISHER STEVEN DEREK , LARSON RICHARD OLIVER , PECK JOHN CHARLES
IPC: G06F13/00 , G06F15/173 , G06F15/16
Abstract: A plurality of multiprocessor systems (a, b ...n) is arranged in a high speed network to allow any processor (10) in one system to communicate with any processor (10) in another system. The network may be configured as a multi- node dual bidirectional ring having a multiprocessor system at each node (18, 20). Packets of information can be passed around the ring in either of two directions and are temporarily stored in buffer memory locations dedicated to a selected destination processor (10) in a selected direction between each successive transfer between neighbouring nodes (18, 20). The buffer locations are managed so that a node (18, 20) can request an adjacent node (18, 20) to stop transmitting packets if the buffer is becoming full from that direction and request resumption of transmission of packets as the buffer empties.
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公开(公告)号：NO833922A
公开(公告)日：1984-04-30
申请号：NO833922
申请日：1983-10-27
Applicant: TANDEM COMPUTERS INC
Inventor： ALLEN JAMES CONARD , BARTLETT WENDY BOHLE , JOHNSON HOKE STEPHENS , FISHER STEVEN DEREK , LARSON RICHARD OLIVER , PECK JOHN CHARLES
IPC: G06F13/00 , G06F15/173 , G06F
CPC classification number: G06F15/17337
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公开(公告)号：GB2114335A
公开(公告)日：1983-08-17
申请号：GB8301359
申请日：1983-01-19
Applicant: TANDEM COMPUTERS INC
Abstract: A memory system (11) for a computer includes logic which detects data errors, address errors and operation errors to increase the reliability of data stored in the memory system. Address errors are detected by encoding address parity information into the data check field of each memory location. A signal is generated in each memory module (21) indicating the status of operations of that memory module and is transmitted to the processor subsystem (13, 15, 17 & 37) of the computer for comparison with a signal indicating the status of operations of the processor subsystem to ensure that all memory modules (21) and the memory control in the processor are receiving the same commands. An interrupt is provided if there is a difference between the commands.
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Patent Agency Ranking
公开(公告)号：DK167416B1
公开(公告)日：1993-10-25
申请号：DK490783
申请日：1983-10-26
Applicant: TANDEM COMPUTERS INC
Inventor： ALLEN JAMES CONARD , BARTLETT WENDY BOHLE , JOHNSON HOKE STEPHENS , FISHER STEVEN DEREK , LARSON RICHARD OLIVER , PECK JOHN CHARLES
IPC: G06F13/00 , G06F15/173 , G06F15/16 , H04L12/46
Abstract: A plurality of multiprocessor systems (a, b ...n) is arranged in a high speed network to allow any processor (10) in one system to communicate with any processor (10) in another system. The network may be configured as a multi- node dual bidirectional ring having a multiprocessor system at each node (18, 20). Packets of information can be passed around the ring in either of two directions and are temporarily stored in buffer memory locations dedicated to a selected destination processor (10) in a selected direction between each successive transfer between neighbouring nodes (18, 20). The buffer locations are managed so that a node (18, 20) can request an adjacent node (18, 20) to stop transmitting packets if the buffer is becoming full from that direction and request resumption of transmission of packets as the buffer empties.
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公开(公告)号：FI80975B
公开(公告)日：1990-04-30
申请号：FI833922
申请日：1983-10-26
Applicant: TANDEM COMPUTERS INC
Inventor： ALLEN JAMES CONARD , BARTLETT WENDY BOHLE , JOHNSON HOKE STEPHENS , FISHER STEVEN DEREK , LARSON RICHARD OLIVER , PECK JOHN CHARLES
IPC: G06F13/00 , G06F15/173 , H04L12/46 , G06F15/16
Abstract: A plurality of multiprocessor systems (a, b ...n) is arranged in a high speed network to allow any processor (10) in one system to communicate with any processor (10) in another system. The network may be configured as a multi- node dual bidirectional ring having a multiprocessor system at each node (18, 20). Packets of information can be passed around the ring in either of two directions and are temporarily stored in buffer memory locations dedicated to a selected destination processor (10) in a selected direction between each successive transfer between neighbouring nodes (18, 20). The buffer locations are managed so that a node (18, 20) can request an adjacent node (18, 20) to stop transmitting packets if the buffer is becoming full from that direction and request resumption of transmission of packets as the buffer empties.
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公开(公告)号：AU560977B2
公开(公告)日：1987-04-30
申请号：AU2066383
申请日：1983-10-27
Applicant: TANDEM COMPUTERS INC
Inventor： ALLEN JAMES CONARD , BARTLETT WENDY BOHLE , JOHNSON HOKE STEPHENS , FISHER STEVEN DEREK , LARSON RICHARD OLIVER , PECK JOHN CHARLES
IPC: G06F13/00 , G06F15/173 , G06F15/16
Abstract: A plurality of multiprocessor systems (a, b ...n) is arranged in a high speed network to allow any processor (10) in one system to communicate with any processor (10) in another system. The network may be configured as a multi- node dual bidirectional ring having a multiprocessor system at each node (18, 20). Packets of information can be passed around the ring in either of two directions and are temporarily stored in buffer memory locations dedicated to a selected destination processor (10) in a selected direction between each successive transfer between neighbouring nodes (18, 20). The buffer locations are managed so that a node (18, 20) can request an adjacent node (18, 20) to stop transmitting packets if the buffer is becoming full from that direction and request resumption of transmission of packets as the buffer empties.
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