公开(公告)号：NO843894L

公开(公告)日：1985-04-01

申请号：NO843894

申请日：1984-09-28

Applicant: TANDEM COMPUTERS INC

Inventor： HARRIS RICHARD LEE ,  HORST ROBERT WHITING

IPC: G06F20060101 ,  G06F9/00 ,  G06F9/22 ,  G06F9/26 ,  G06F9/38 ,  G06F9/40 ,  G06F9/42 ,  G06F

Abstract: Hardware for performing microcode branching in a central processing unit allows for two different speeds of branches which can be used by microcode and includes flexibility to optionally inhibit the extra lines which enter the pipeline on a branch. A default branch path can be taken for a test result not yet available and can be replaced with a correct branch target during a clock pause if the test result is false. A return address stack is provided with decoupled loading and pushing to accommodate the two branching speeds. Microcode can specify loading the return address stack with a literal or register value to allow vectored branching and returning to a desired line after a delayed call.

公开(公告)号：NO843893A

公开(公告)日：1985-04-01

申请号：NO843893

申请日：1984-09-28

Applicant: TANDEM COMPUTERS INC

Inventor： HARRIS RICHARD LEE ,  HORST ROBERT WHITING

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/28 ,  G06F9/38 ,  G06F

CPC classification number: G06F9/261 ,  G06F9/267

公开(公告)号：FI843782L

公开(公告)日：1985-03-30

申请号：FI843782

申请日：1984-09-26

Applicant: TANDEM COMPUTERS INC

Inventor： HORST ROBERT WHITING ,  HARRIS RICHARD LEE

IPC: G06F20060101 ,  G06F9/00 ,  G06F9/22 ,  G06F9/26 ,  G06F9/38 ,  G06F9/40 ,  G06F9/42 ,  G06F

Abstract: Hardware for performing microcode branching in a central processing unit allows for two different speeds of branches which can be used by microcode and includes flexibility to optionally inhibit the extra lines which enter the pipeline on a branch. A default branch path can be taken for a test result not yet available and can be replaced with a correct branch target during a clock pause if the test result is false. A return address stack is provided with decoupled loading and pushing to accommodate the two branching speeds. Microcode can specify loading the return address stack with a literal or register value to allow vectored branching and returning to a desired line after a delayed call.