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    1.
    发明专利
    未知

    公开(公告)号：FI85428B

    公开(公告)日：1991-12-31

    申请号：FI843781

    申请日：1984-09-26

    Applicant: TANDEM COMPUTERS INC

    Inventor： HORST ROBERT WHITING ,  LYNCH SHANNON JOSEPH ,  COSTANTINO CIRILLO LINO ,  BEIRNE JOHN MARTIN

    IPC: G06F7/00 ,  G06F9/30 ,  G06F9/38

    Abstract: The various functional units which comprise a central pro- cessing unit of a computer are organized so as to enable a main arithmetic logic unit and special function units including an auxilliary arithmetic logic unit to access data registers, literal constants, and data from a memory cache. A general purpose bus closely couples the functional units to the main data paths and allows the CPU sequencer to branch on numerous conditions which may be indicated via test lines. Parity from the functional units is sent a clock cycle later than results in order that the parity path does not affect machine cycle time. The architecture allows unused microcode options to be used to check for correct CPU operation by halting CPU operation on a miscompare of two buses.

    2.
    发明专利
    未知

    公开(公告)号：DE3482607D1

    公开(公告)日：1990-08-02

    申请号：DE3482607

    申请日：1984-09-28

    Applicant: TANDEM COMPUTERS INC

    Inventor： HARRIS RICHARD LEE ,  HORST ROBERT WHITING

    IPC: G06F9/22 ,  G06F9/26 ,  G06F9/28 ,  G06F9/38

    Abstract: g An entry control store in a central processing unit (CPU) is addressed by the next macroinstruction to be executed by the CPU and fetches the microcode for the first line of that macroinstruction.The apparatus includes an entry point table (42) and a control store (58) wherein, in macroinstruction access a pointer in the entry point table is used to obtain microcode from the control store (58) and place it on a bus (62) connected to output lines of the control store (58). An auxilliary control store (48), containing the first line of microcode for each macroinstruction, is accessed by the microinstructions and has output lines which are selectably connected to the bus (62) by bus selection means (84) for selectively disconnecting the output lines of the control store (58) from the bus (62) when the output lines of auxilliary control store (48) are selectably connected to the bus (62). The selection means (84) are arranged to respond to microcode indicia (80) indicating whether the control store (58) or the auxilliary control store (48) are to be connected to the bus (62).

    3.
    发明专利
    未知

    公开(公告)号：BR8404921A

    公开(公告)日：1985-08-20

    申请号：BR8404921

    申请日：1984-09-28

    Applicant: TANDEM COMPUTERS INC

    Inventor： HORST ROBERT WHITING ,  HARRIS RICHARD LEE

    IPC: G06F20060101 ,  G06F9/00 ,  G06F9/22 ,  G06F9/26 ,  G06F9/38 ,  G06F9/40 ,  G06F9/42 ,  G06F11/00

    Abstract: Hardware for performing microcode branching in a central processing unit allows for two different speeds of branches which can be used by microcode and includes flexibility to optionally inhibit the extra lines which enter the pipeline on a branch. A default branch path can be taken for a test result not yet available and can be replaced with a correct branch target during a clock pause if the test result is false. A return address stack is provided with decoupled loading and pushing to accommodate the two branching speeds. Microcode can specify loading the return address stack with a literal or register value to allow vectored branching and returning to a desired line after a delayed call.

    ENHANCED CPU MICROBRANCHING ARCHITECTURE
    5.
    发明专利
    ENHANCED CPU MICROBRANCHING ARCHITECTURE 未知

    公开(公告)号：AU3359384A

    公开(公告)日：1985-04-04

    申请号：AU3359384

    申请日：1984-09-27

    Applicant: TANDEM COMPUTERS INC

    Inventor： HORST ROBERT WHITING ,  HARRIS RICHARD LEE

    IPC: G06F20060101 ,  G06F9/00 ,  G06F9/22 ,  G06F9/26 ,  G06F9/38 ,  G06F9/40 ,  G06F9/42

    Abstract: Hardware for performing microcode branching in a central processing unit allows for two different speeds of branches which can be used by microcode and includes flexibility to optionally inhibit the extra lines which enter the pipeline on a branch. A default branch path can be taken for a test result not yet available and can be replaced with a correct branch target during a clock pause if the test result is false. A return address stack is provided with decoupled loading and pushing to accommodate the two branching speeds. Microcode can specify loading the return address stack with a literal or register value to allow vectored branching and returning to a desired line after a delayed call.

    7.
    发明专利
    未知

    公开(公告)号：NO843893L

    公开(公告)日：1985-04-01

    申请号：NO843893

    申请日：1984-09-28

    Applicant: TANDEM COMPUTERS INC

    Inventor： HARRIS RICHARD LEE ,  HORST ROBERT WHITING

    IPC: G06F9/22 ,  G06F9/26 ,  G06F9/28 ,  G06F9/38 ,  G06F

    Abstract: g An entry control store in a central processing unit (CPU) is addressed by the next macroinstruction to be executed by the CPU and fetches the microcode for the first line of that macroinstruction.The apparatus includes an entry point table (42) and a control store (58) wherein, in macroinstruction access a pointer in the entry point table is used to obtain microcode from the control store (58) and place it on a bus (62) connected to output lines of the control store (58). An auxilliary control store (48), containing the first line of microcode for each macroinstruction, is accessed by the microinstructions and has output lines which are selectably connected to the bus (62) by bus selection means (84) for selectively disconnecting the output lines of the control store (58) from the bus (62) when the output lines of auxilliary control store (48) are selectably connected to the bus (62). The selection means (84) are arranged to respond to microcode indicia (80) indicating whether the control store (58) or the auxilliary control store (48) are to be connected to the bus (62).

    10.
    发明专利
    未知

    公开(公告)号：DK462684D0

    公开(公告)日：1984-09-27

    申请号：DK462684

    申请日：1984-09-27

    Applicant: TANDEM COMPUTERS INC

    Inventor： HORST ROBERT WHITING ,  HARRIS RICHARD LEE

    IPC: G06F20060101 ,  G06F9/00 ,  G06F9/22 ,  G06F9/26 ,  G06F9/38 ,  G06F9/40 ,  G06F9/42 ,  G06F

    Abstract: Hardware for performing microcode branching in a central processing unit allows for two different speeds of branches which can be used by microcode and includes flexibility to optionally inhibit the extra lines which enter the pipeline on a branch. A default branch path can be taken for a test result not yet available and can be replaced with a correct branch target during a clock pause if the test result is false. A return address stack is provided with decoupled loading and pushing to accommodate the two branching speeds. Microcode can specify loading the return address stack with a literal or register value to allow vectored branching and returning to a desired line after a delayed call.

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