公开(公告)号：JPS60167036A

公开(公告)日：1985-08-30

申请号：JP20389784

申请日：1984-09-28

Applicant: TANDEM COMPUTERS INC

Inventor： WHITING HORST ROBERT ,  HARRIS RICHARD LEE

IPC: G06F20060101 ,  G06F9/00 ,  G06F9/22 ,  G06F9/26 ,  G06F9/38 ,  G06F9/40 ,  G06F9/42

公开(公告)号：AT54212T

公开(公告)日：1990-07-15

申请号：AT84306610

申请日：1984-09-28

Applicant: TANDEM COMPUTERS INC

Inventor： HARRIS RICHARD LEE ,  HORST ROBERT WHITING

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/28 ,  G06F9/38

Abstract: g An entry control store in a central processing unit (CPU) is addressed by the next macroinstruction to be executed by the CPU and fetches the microcode for the first line of that macroinstruction.The apparatus includes an entry point table (42) and a control store (58) wherein, in macroinstruction access a pointer in the entry point table is used to obtain microcode from the control store (58) and place it on a bus (62) connected to output lines of the control store (58). An auxilliary control store (48), containing the first line of microcode for each macroinstruction, is accessed by the microinstructions and has output lines which are selectably connected to the bus (62) by bus selection means (84) for selectively disconnecting the output lines of the control store (58) from the bus (62) when the output lines of auxilliary control store (48) are selectably connected to the bus (62). The selection means (84) are arranged to respond to microcode indicia (80) indicating whether the control store (58) or the auxilliary control store (48) are to be connected to the bus (62).

公开(公告)号：AU599245B2

公开(公告)日：1990-07-12

申请号：AU1830088

申请日：1988-06-23

Applicant: TANDEM COMPUTERS INC

Inventor： HORST ROBERT WHITING ,  HARRIS RICHARD LEE

IPC: G06F20060101 ,  G06F9/00 ,  G06F9/22 ,  G06F9/26 ,  G06F9/38 ,  G06F9/40 ,  G06F9/42

Abstract: Hardware for performing microcode branching in a central processing unit allows for two different speeds of branches which can be used by microcode and includes flexibility to optionally inhibit the extra lines which enter the pipeline on a branch. A default branch path can be taken for a test result not yet available and can be replaced with a correct branch target during a clock pause if the test result is false. A return address stack is provided with decoupled loading and pushing to accommodate the two branching speeds. Microcode can specify loading the return address stack with a literal or register value to allow vectored branching and returning to a desired line after a delayed call.

公开(公告)号：DK462684A

公开(公告)日：1985-03-30

申请号：DK462684

申请日：1984-09-27

Applicant: TANDEM COMPUTERS INC

Inventor： HORST ROBERT WHITING ,  HARRIS RICHARD LEE

IPC: G06F20060101 ,  G06F9/00 ,  G06F9/22 ,  G06F9/26 ,  G06F9/38 ,  G06F9/40 ,  G06F9/42 ,  G06F

Abstract: Hardware for performing microcode branching in a central processing unit allows for two different speeds of branches which can be used by microcode and includes flexibility to optionally inhibit the extra lines which enter the pipeline on a branch. A default branch path can be taken for a test result not yet available and can be replaced with a correct branch target during a clock pause if the test result is false. A return address stack is provided with decoupled loading and pushing to accommodate the two branching speeds. Microcode can specify loading the return address stack with a literal or register value to allow vectored branching and returning to a desired line after a delayed call.

公开(公告)号：AU577316B2

公开(公告)日：1988-09-22

申请号：AU3359384

申请日：1984-09-27

Applicant: TANDEM COMPUTERS INC

Inventor： HORST ROBERT WHITING ,  HARRIS RICHARD LEE

IPC: G06F20060101 ,  G06F9/00 ,  G06F9/22 ,  G06F9/26 ,  G06F9/38 ,  G06F9/40 ,  G06F9/42

Abstract: Hardware for performing microcode branching in a central processing unit allows for two different speeds of branches which can be used by microcode and includes flexibility to optionally inhibit the extra lines which enter the pipeline on a branch. A default branch path can be taken for a test result not yet available and can be replaced with a correct branch target during a clock pause if the test result is false. A return address stack is provided with decoupled loading and pushing to accommodate the two branching speeds. Microcode can specify loading the return address stack with a literal or register value to allow vectored branching and returning to a desired line after a delayed call.

公开(公告)号：DE3485172D1

公开(公告)日：1991-11-21

申请号：DE3485172

申请日：1984-09-27

Applicant: TANDEM COMPUTERS INC

Inventor： HORST ROBERT WHITING ,  HARRIS RICHARD LEE

IPC: G06F20060101 ,  G06F9/00 ,  G06F9/22 ,  G06F9/26 ,  G06F9/38 ,  G06F9/40 ,  G06F9/42

Abstract: Hardware for performing microcode branching in a central processing unit allows for two different speeds of branches which can be used by microcode and includes flexibility to optionally inhibit the extra lines which enter the pipeline on a branch. A default branch path can be taken for a test result not yet available and can be replaced with a correct branch target during a clock pause if the test result is false. A return address stack is provided with decoupled loading and pushing to accommodate the two branching speeds. Microcode can specify loading the return address stack with a literal or register value to allow vectored branching and returning to a desired line after a delayed call.

公开(公告)号：AU1830088A

公开(公告)日：1988-10-27

申请号：AU1830088

申请日：1988-06-23

Applicant: TANDEM COMPUTERS INC

Inventor： HORST ROBERT WHITING ,  HARRIS RICHARD LEE

IPC: G06F20060101 ,  G06F9/00 ,  G06F9/22 ,  G06F9/26 ,  G06F9/38 ,  G06F9/40 ,  G06F9/42

Abstract: Hardware for performing microcode branching in a central processing unit allows for two different speeds of branches which can be used by microcode and includes flexibility to optionally inhibit the extra lines which enter the pipeline on a branch. A default branch path can be taken for a test result not yet available and can be replaced with a correct branch target during a clock pause if the test result is false. A return address stack is provided with decoupled loading and pushing to accommodate the two branching speeds. Microcode can specify loading the return address stack with a literal or register value to allow vectored branching and returning to a desired line after a delayed call.

公开(公告)号：IN162544B

公开(公告)日：1988-06-11

申请号：IN693CA1984

申请日：1984-09-27

Applicant: TANDEM COMPUTERS INC

Inventor： WHITING HORST ROBERT ,  HARRIS RICHARD LEE

IPC: G06F20060101 ,  G06F9/00 ,  G06F9/22 ,  G06F9/26 ,  G06F9/38 ,  G06F9/40 ,  G06F9/42 ,  G06K17/00

Abstract: Hardware for performing microcode branching in a central processing unit allows for two different speeds of branches which can be used by microcode and includes flexibility to optionally inhibit the extra lines which enter the pipeline on a branch. A default branch path can be taken for a test result not yet available and can be replaced with a correct branch target during a clock pause if the test result is false. A return address stack is provided with decoupled loading and pushing to accommodate the two branching speeds. Microcode can specify loading the return address stack with a literal or register value to allow vectored branching and returning to a desired line after a delayed call.

公开(公告)号：AU571010B2

公开(公告)日：1988-03-31

申请号：AU3359484

申请日：1984-09-27

Applicant: TANDEM COMPUTERS INC

Inventor： HARRIS RICHARD LEE ,  HORST ROBERT WHITING

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/28 ,  G06F9/38

Abstract: g An entry control store in a central processing unit (CPU) is addressed by the next macroinstruction to be executed by the CPU and fetches the microcode for the first line of that macroinstruction.The apparatus includes an entry point table (42) and a control store (58) wherein, in macroinstruction access a pointer in the entry point table is used to obtain microcode from the control store (58) and place it on a bus (62) connected to output lines of the control store (58). An auxilliary control store (48), containing the first line of microcode for each macroinstruction, is accessed by the microinstructions and has output lines which are selectably connected to the bus (62) by bus selection means (84) for selectively disconnecting the output lines of the control store (58) from the bus (62) when the output lines of auxilliary control store (48) are selectably connected to the bus (62). The selection means (84) are arranged to respond to microcode indicia (80) indicating whether the control store (58) or the auxilliary control store (48) are to be connected to the bus (62).

公开(公告)号：AU3359484A

公开(公告)日：1985-04-04

申请号：AU3359484

申请日：1984-09-27

Applicant: TANDEM COMPUTERS INC

Inventor： HARRIS RICHARD LEE ,  HORST ROBERT WHITING

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/28 ,  G06F9/38

Abstract: g An entry control store in a central processing unit (CPU) is addressed by the next macroinstruction to be executed by the CPU and fetches the microcode for the first line of that macroinstruction.The apparatus includes an entry point table (42) and a control store (58) wherein, in macroinstruction access a pointer in the entry point table is used to obtain microcode from the control store (58) and place it on a bus (62) connected to output lines of the control store (58). An auxilliary control store (48), containing the first line of microcode for each macroinstruction, is accessed by the microinstructions and has output lines which are selectably connected to the bus (62) by bus selection means (84) for selectively disconnecting the output lines of the control store (58) from the bus (62) when the output lines of auxilliary control store (48) are selectably connected to the bus (62). The selection means (84) are arranged to respond to microcode indicia (80) indicating whether the control store (58) or the auxilliary control store (48) are to be connected to the bus (62).