公开(公告)号：DE19757119A1

公开(公告)日：1999-07-01

申请号：DE19757119

申请日：1997-12-20

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YANG MING-SHENG ,  WU JUAN-YUAN ,  LUR WATER ,  SUN SHIH-WEI

IPC: C09K3/14 ,  H01L21/321 ,  H01L21/302 ,  B24B37/04 ,  H01L21/768

Abstract: Chemical mechanical polishing, of a semiconductor wafer with a tungsten layer (38) on a dielectric layer (32), uses a single polishing pad (44) and a first slurry mixture (42) containing an oxidising agent to polish the tungsten and expose the dielectric layer. A second slurry mixture containing an oxide etchant is then used to polish the dielectric. Both slurry mixtures have a pH of 2-4. The first slurry includes water, Fe(NO3)3, Al2O3, H2O2, and may also contain KIO3.

公开(公告)号：GB2330002A

公开(公告)日：1999-04-07

申请号：GB9721154

申请日：1997-10-06

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH-WEI ,  YEW TRI-RUNG

IPC: H01L21/8242 ,  H01L27/108

Abstract: Transfer FETs and wiring lines are provided for the embedded DRAM circuits and FETs are provided for the logic portions of the device. A thin, conformal oxide protection layer 129 is provided over the surface of the device to cover the transfer FETs and the logic FETs to protect portions of the device during formation of the charge storage capacitors. A mask is provided having openings over the appropriate source/drain regions of the transfer FETs and the oxide layer is etched. A planar or substantially planar lower capacitor electrode is defined by providing and patterning a first layer of doped polysilicon over the thin protective oxide layer in contact with the desired source/drain regions of the transfer FETs. Tantalum pentoxide or barium strantium titanate might be used as the capacitor dielectric to provide the needed capacitance for the cells of the embedded DRAM array. An upper capacitor electrode is provided and the protective oxide layer is removed from the logic circuits. Because the protective oxide layer is thinner and more uniform than is conventional, it is easier to perform this etching step without damaging the FETs of the logic circuit. A conventional salicide process can then be used to complete formation of the FETs of the logic circuits of the device.

公开(公告)号：DE19801854A1

公开(公告)日：1999-01-07

申请号：DE19801854

申请日：1998-01-20

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YEW TRI-RUNG ,  LUR WATER ,  SUN SHIH-WEI

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/8242

Abstract: A DRAM production process involves (a) producing a transistor with a gate, a source/drain region and a word line on a silicon substrate; (b) covering the transistor with an oxide layer and producing a via in the layer to expose the source/drain region surface; (c) producing a conductive layer in the via to cover the oxide layer and structuring the conductive layer to produce a lower electrode connected to the source/drain region; (d) producing a dielectric layer over the lower electrode and the oxide layer; (e) covering the dielectric layer with an upper electrode; and (f) producing, on the upper electrode, a titanium layer and then a dielectric inter-level layer. Also claimed is a DRAM production process involving the above steps (d), (e) and (f).

公开(公告)号：NL1006172C2

公开(公告)日：1998-12-01

申请号：NL1006172

申请日：1997-05-30

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH-WEI ,  YEW TRI-RUNG

IPC: H01L21/3205 ,  H01L21/306 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78

Abstract: A method of forming a DRAM includes forming a transfer FET on a substrate, the FET having a gate on a gate oxide layer above the substrate and a first and second source/drain region in the substrate on either side of a channel region under the gate. The first and second source/drain regions are typically exposed or nearly exposed in a spacer etch process. A silicon nitride etch stop layer is deposited over the entire structure and then a thick layer of oxide is deposited on the device. Chemical mechanical polishing is performed to provide a planar surface on the thick oxide layer. An opening is formed through the thick layer of oxide above the first source/drain region, stopping at the etch stop layer. The etch stop layer is removed within the opening in the thick layer of oxide and the underlying thin oxide layer is etched. A capacitor electrode can then be formed in contact with the exposed portion of the first source/drain region. A similar self-aligned method can be used to form the bit line contact for the device using the etch stop layer as a stop for the bit line contact etch. Practice of the method provides a manufacturing method having improved reliability and ease of use, particularly when practiced for DRAM capacitors that incorporate high dielectric constant dielectrics. The materials preferred for use within such DRAM capacitors have smaller process margins and so particularly benefit from the improved structure and process.

公开(公告)号：DE19719699A1

公开(公告)日：1998-11-12

申请号：DE19719699

申请日：1997-05-09

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH-WEI ,  YEW TRI-RUNG

IPC: H01L21/3205 ,  H01L21/306 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78

Abstract: Formation of a dynamic random access memory (DRAM) comprises (i) providing an insulating layer over an active region of a substrate (50), (ii) forming transfer transistors on the active region, the first transistor including a gate electrode over the insulating layer and first and second source/drain regions (82, 84) formed in the substrate, the second transistor including a second gate electrode over the insulating layer and the second and third source/drain regions, the transistors sharing the second source/drain region, (ii) forming an etch stop layer (90) over the first and second gate electrodes and over the first, second and third source/drain regions, (iii) forming a dielectric layer (96) over the etch stop layer, (iv) etching through the dielectric layer above the second source/drain region, stopping the etching process on the etch stop layer, performing a further etching process to etch through the etch stop layer and then forming a bit line contact (112) to the second source/drain region, and (v) etching through the dielectric layer above the third source/drain region, stopping the etching process on the etch stop layer, performing a further etching process to etch through the etch stop layer and then forming a charge storage capacitor having an electrode (98) electrically connected to the third source/drain region and comprising a layer of hemispherical grained polysilicon.

公开(公告)号：GB2325083A

公开(公告)日：1998-11-11

申请号：GB9709431

申请日：1997-05-09

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YEW TRI-RUNG ,  LIU MONG-CHUNG ,  LUR WATER ,  SUN SHIH-WEI

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/52

Abstract: A dual damascene process forms a two level metal interconnect structure by first providing a interlayer oxide 52 over a device structure 50 and covering the interlevel oxide layer with an etch stop layer 54. The etch stop layer is patterned to form tapered openings 72 corresponding to the pattern of the interconnects that are to be formed in the first level of the two level interconnect structure. After the etch stop layer is patterned, an intermetal oxide layer 56 is provided over the etch stop layer. Because the etch stop layer is relatively thin, the topography formed on the surface of the intermetal oxide layer is relatively small. A photoresist mask is then provided over the intermetal oxide layer with openings in the mask exposing portions of the intermetal oxide layer in the pattern of the wiring lines to be provided in the second level of the interconnect structure. The intermetal oxide layer is etched and the etching process continues to form openings in the interlayer oxide where the interlayer oxide is exposed by the openings in the etch stop layer. Thus, in a single etching step, the openings for both the second level wiring lines and the first level interconnects are defined. Metal is then deposited over the structure and excess metal is removed by chemical mechanical polishing to define the two level interconnect structure.

公开(公告)号：GB2324408A8

公开(公告)日：1998-10-26

申请号：GB9707790

申请日：1997-04-17

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH-WEI ,  YEW TRI-RUNG

IPC: H01L21/3205 ,  H01L21/306 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78

Abstract: A method of forming a DRAM includes forming a transfer FET on a substrate, the FET having a gate on a gate oxide layer above the substrate and a first and second source/drain region in the substrate on either side of a channel region under the gate. The first and second source/drain regions are typically exposed or nearly exposed in a spacer etch process. A silicon nitride etch stop layer is deposited over the entire structure and then a thick layer of oxide is deposited on the device. Chemical mechanical polishing is performed to provide a planar surface on the thick oxide layer. An opening is formed through the thick layer of oxide above the first source/drain region, stopping at the etch stop layer. The etch stop layer is removed within the opening in the thick layer of oxide and the underlying thin oxide layer is etched. A capacitor electrode can then be formed in contact with the exposed portion of the first source/drain region. A similar self-aligned method can be used to form the bit line contact for the device using the etch stop layer as a stop for the bit line contact etch. Practice of the method provides a manufacturing method having improved reliability and ease of use, particularly when practiced for DRAM capacitors that incorporate high dielectric constant dielectrics. The materials preferred for use within such DRAM capacitors have smaller process margins and so particularly benefit from the improved structure and process.

公开(公告)号：DE19710961A1

公开(公告)日：1998-09-24

申请号：DE19710961

申请日：1997-03-17

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH-WEI

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/321 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: Producing memory device on substrate, which has a charge storage capacitor, includes the following: - Provide a transistor, which has already formed source/drain and gate electrode on its surface; - Deposit 1st insulating layer on transistor; - Deposit 2nd insulating layer, which has different material with 1st insulating, on 1st insulating layer; - Through 1st and 2nd insulating layer to provide 1st contact window to expose 1st source/drain of transistor; - Deposit 1st polysilicon on 2nd insulating layer, the 1st polysilicon is doing electrical contact with 1st source/drain of transistor; - Deposit 3rd insulating layer on 1st polysilicon layer, and image 3rd insulating layer to provide 2nd contact window to expose 1st polysilicon layer; - Deposit 2nd polysilicon to fill 2nd contact window; - Proceed polishing to remove redundant part of 2nd polysilicon; - Remove 3rd insulating layer to expose polysilicon superstructure vertically extended on 1st polysilicon layer, and form portion of bottom electrode of charge storage capacitor; - Form dielectric on top of polysilicon superstructure and 1st polysilicon layer; - Deposit 3rd polysilicon layer, and form upper electrode of charge storage capacitor.

公开(公告)号：NL1004811C2

公开(公告)日：1998-06-19

申请号：NL1004811

申请日：1996-12-18

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH-WEI ,  YEW TRI-RUNG ,  LUR WATER

IPC: H01L21/02 ,  H01L21/8239 ,  H01L21/3205

Abstract: Manufacture of semiconductor device comprises (1) supplying one silicon layer, overlaying one silicon substrate or on the silicon substrate; (2) on the silicon layer supplying one first hemispherical silicon grain layer; (3) on the first hemispherical silicon grain layer depositing one second hemispherical silicon grain layer, in which the first hemispherical silicon grain layer consists of multiple first hemispherical silicon grains, the second hemispherical silicon grain layer consists of multiple second hemispherical silicon grains, and making those second hemispherical silicon grains be able to grow on those first hemispherical silicon grains.

公开(公告)号：DE19651832A1

公开(公告)日：1998-06-18

申请号：DE19651832

申请日：1996-12-13

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH-WEI ,  YEW TRI-RUNG ,  LUR WATER

IPC: H01L21/02 ,  H01L21/205 ,  H01L21/8242

Abstract: The capacitor, e.g. of a DRAM cell, is formed by depositing a first layer of hemispherical-grained silicon (HSG-Si) 42 on a substrate such as a layer of doped polysilicon 40 e.g. by LPCVD. Growth of the first layer of HSG-Si is interrupted and then a second layer of HSG-Si 46,48 grown independently of the first layer. In one aspect, growth of the first layer of HSG-Si may be interrupted by either cooling the deposition substrate or stopping deposition for a period of time. The interruption of the growth of the first layer is sufficient to ensure that the reinitiated growth initiates in a manner that is independent of the first process. In a different aspect of the invention, growth of the first layer may be interrupted deposition of amorphous silicon or by removing the substrate from the deposition system and performing an etch back operation. After the etch back operation, the substrate is reintroduced to the deposition system and a second layer of HSG-Si is grown on the etched surface. This textured silicon structure forms the lower electrode of the DRAM capacitor.