公开(公告)号：US09064931B2

公开(公告)日：2015-06-23

申请号：US13649126

申请日：2012-10-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/485 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76816 ,  H01L21/76807 ,  H01L23/485 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a semiconductor structure including at least a contact plug. The structure includes a substrate, a transistor, a first ILD layer, a second ILD layer and a first contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor and levels with a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The first contact plug is disposed in the first ILD layer and the second ILD layer and includes a first trench portion and a first via portion, wherein a boundary of the first trench portion and a first via portion is higher than the top surface of the gate. The present invention further provides a method of making the same.

Abstract translation: 本发明提供至少包括接触插头的半导体结构。 该结构包括衬底，晶体管，第一ILD层，第二ILD层和第一接触插塞。 晶体管设置在衬底上并且包括栅极和源极/漏极区域。 第一ILD层设置在晶体管上并且与栅极的顶表面平齐。 第二ILD层设置在第一ILD层上。 第一接触插塞设置在第一ILD层和第二ILD层中，并且包括第一沟槽部分和第一通孔部分，其中第一沟槽部分和第一通孔部分的边界高于栅极的顶表面 。 本发明还提供了制备该方法的方法。

公开(公告)号：US20150145027A1

公开(公告)日：2015-05-28

申请号：US14091349

申请日：2013-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Jia-Rong Wu ,  Ching-Wen Hung

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/785

Abstract: A method for fabricating a semiconductor device is provided according to one embodiment of the present invention and includes forming an interlayer dielectric on a substrate; forming a trench surrounded by the interlayer dielectric; depositing a dielectric layer and a work function layer on a surface of the trench sequentially and conformally; filling up the trench with a conductive layer; removing an upper portion of the conductive layer inside the trench; forming a protection film on a top surface of the interlayer dielectric and a top surface of the conductive layer through a directional deposition process; removing the dielectric layer exposed from the protection film; and forming a hard mask to cover the protection film.

Abstract translation: 根据本发明的一个实施例提供一种制造半导体器件的方法，包括在衬底上形成层间电介质; 形成由层间电介质包围的沟槽; 依次和保形地在沟槽的表面上沉积介电层和功函数层; 用导电层填充沟槽; 去除沟槽内的导电层的上部; 通过定向沉积工艺在层间电介质的顶表面和导电层的顶表面上形成保护膜; 去除从保护膜暴露的电介质层; 并形成硬掩模以覆盖保护膜。

公开(公告)号：US09006804B2

公开(公告)日：2015-04-14

申请号：US13912173

申请日：2013-06-06

Applicant: United Microelectronics Corp.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao ,  Shih-Fang Tzou

IPC: H01L29/76 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L21/28079 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32053 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor device is provided herein and includes the following steps. First, a first interlayer dielectric is formed on a substrate. Then, a gate electrode is formed on the substrate, wherein a periphery of the gate electrode is surrounded by the first interlayer dielectric. Afterwards, a patterned mask layer is formed on the gate electrode, wherein a bottom surface of the patterned mask layer is leveled with a top surface of the first interlayer dielectric. A second interlayer dielectric is then formed to cover a top surface and each side surface of the patterned mask layer. Finally, a self-aligned contact structure is formed in the first interlayer dielectric and the second interlayer dielectric.

Abstract translation: 本发明提供一种制造半导体器件的方法，包括以下步骤。 首先，在基板上形成第一层间电介质。 然后，在基板上形成栅电极，其中栅电极的周围被第一层间电介质包围。 之后，在栅电极上形成图案化掩模层，其中图案化掩模层的底表面与第一层间电介质的顶表面平齐。 然后形成第二层间电介质以覆盖图案化掩模层的顶表面和每个侧表面。 最后，在第一层间电介质和第二层间电介质中形成自对准接触结构。

公开(公告)号：US09006110B1

公开(公告)日：2015-04-14

申请号：US14074720

申请日：2013-11-08

Applicant: United Microelectronics Corp.

Inventor： Chien-Ying Sun ,  En-Chiuan Liou ,  Jia-Rong Wu ,  Ching-Wen Hung

IPC: H01L21/311 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/308

CPC classification number: H01L21/30604 ,  H01L21/3083 ,  H01L21/823431

Abstract: A method for fabricating a patterned structure of a semiconductor device includes: forming first mandrels and second mandrels on a substrate, wherein a first spacing is defined between the two adjacent first mandrels and a second spacing is defined between the two adjacent second mandrels, the first spacing being wider than the second spacing; forming a cover layer to cover the first mandrels while exposing the second mandrels; etching the cover layer and the second mandrels; removing the cover layer; concurrently forming first spacers on the sides of the first mandrels and a second spacers on the sides of the second mandrels after removing the cover layer; and transferring a layout of the first and second spacers to the substrate so as to form fin-shaped structures.

Abstract translation: 一种用于制造半导体器件的图案化结构的方法包括：在衬底上形成第一心轴和第二心轴，其中在所述两个相邻的第一心轴之间限定第一间隔，并且在所述两个相邻的第二心轴之间限定第二间距， 间隔宽于第二间距; 形成覆盖层以覆盖所述第一心轴同时暴露所述第二心轴; 蚀刻覆盖层和第二芯棒; 去除覆盖层; 在去除覆盖层之后，同时在第一心轴的侧面上形成第一间隔物和在第二心轴的侧面上的第二间隔物; 以及将所述第一和第二间隔物的布局转移到所述基底以形成鳍状结构。

公开(公告)号：US08962490B1

公开(公告)日：2015-02-24

申请号：US14048043

申请日：2013-10-08

Applicant: United Microelectronics Corp.

Inventor： Ching-Wen Hung ,  Jia-Rong Wu ,  Chih-Sen Huang ,  Chieh-Te Chen

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L21/76814 ,  H01L21/02063 ,  H01L21/76802 ,  H01L29/66477

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon, wherein at least one metal gate is formed in the ILD layer and at least one source/drain region is adjacent to two sides of the metal gate; forming a first dielectric layer on the ILD layer; forming a second dielectric layer on the first dielectric layer; performing a first etching process to partially remove the second dielectric layer; utilizing a first cleaning agent for performing a first wet clean process; performing a second etching process to partially remove the first dielectric layer; and utilizing a second cleaning agent for performing a second wet clean process, wherein the first cleaning agent is different from the second cleaning agent.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有层间电介质（ILD）层的衬底，其中至少一个金属栅极形成在ILD层中，并且至少一个源极/漏极区域邻近金属栅极的两侧; 在ILD层上形成第一介电层; 在所述第一电介质层上形成第二电介质层; 执行第一蚀刻工艺以部分地去除所述第二介电层; 利用第一清洁剂进行第一次湿清洁处理; 执行第二蚀刻工艺以部分地去除所述第一介电层; 并且利用第二清洁剂进行第二湿式清洁处理，其中所述第一清洁剂与所述第二清洁剂不同。

公开(公告)号：US20140327080A1

公开(公告)日：2014-11-06

申请号：US13875293

申请日：2013-05-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/665 ,  H01L21/76814 ,  H01L21/76879 ,  H01L29/41791 ,  H01L29/66515 ,  H01L29/66795 ,  H01L29/7839 ,  H01L29/785

Abstract: The present invention provides a manufacturing method of a semiconductor structure, comprising the following steps. First, a substrate is provided, a first dielectric layer is formed on the substrate, a metal gate is disposed in the first dielectric layer and at least one source/drain region (S/D region) is disposed on two sides of the metal gate, a second dielectric layer is then formed on the first dielectric layer, a first etching process is then performed to form a plurality of first trenches in the first dielectric layer and the second dielectric layer, wherein the first trenches expose each S/D region. Afterwards, a salicide process is performed to form a salicide layer in each first trench, a second etching process is then performed to form a plurality of second trenches in the first dielectric layer and the second dielectric layer, and the second trenches expose the metal gate.

Abstract translation: 本发明提供一种半导体结构的制造方法，包括以下步骤。 首先，提供基板，在基板上形成第一介电层，金属栅极设置在第一介电层中，并且至少一个源极/漏极区（S / D区）设置在金属栅极的两侧 然后在第一介电层上形成第二电介质层，然后执行第一蚀刻工艺以在第一电介质层和第二电介质层中形成多个第一沟槽，其中第一沟槽暴露每个S / D区域。 然后，进行自对准处理以在每个第一沟槽中形成自对准硅化物层，然后执行第二蚀刻工艺以在第一介电层和第二介电层中形成多个第二沟槽，并且第二沟槽暴露金属栅极 。

公开(公告)号：US20140284671A1

公开(公告)日：2014-09-25

申请号：US13848736

申请日：2013-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao

IPC: H01L49/02 ,  H01L21/28 ,  H01L27/06

CPC classification number: H01L27/0629 ,  H01L21/28 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/1085 ,  H01L28/60 ,  H01L28/75 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66477 ,  H01L29/66545

Abstract: A semiconductor structure includes a metal gate, a second dielectric layer and a contact plug. The metal gate is located on a substrate and in a first dielectric layer, wherein the metal gate includes a work function metal layer having a U-shaped cross- sectional profile and a low resistivity material located on the work function metal layer. The second dielectric layer is located on the metal gate and the first dielectric layer. The contact plug is located on the second dielectric layer and in a third dielectric layer, thereby a capacitor is formed. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.

Abstract translation: 半导体结构包括金属栅极，第二电介质层和接触插塞。 金属栅极位于基板和第一电介质层中，其中金属栅极包括具有U形横截面轮廓的功函数金属层和位于功函数金属层上的低电阻率材料。 第二电介质层位于金属栅极和第一电介质层上。 接触塞位于第二电介质层上，在第三电介质层中形成电容器。 此外，本发明还提供了形成所述半导体结构的半导体工艺。

公开(公告)号：US12279535B2

公开(公告)日：2025-04-15

申请号：US18511984

申请日：2023-11-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Ya-Sheng Feng

IPC: H10N50/80 ,  H01L21/768 ,  H10N50/01

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; removing the sacrificial layer to form a recess; forming a barrier layer and a free layer in the recess; forming a top electrode layer on the free layer; and patterning the top electrode layer and the free layer to form a second MTJ.

公开(公告)号：US20240222369A1

公开(公告)日：2024-07-04

申请号：US18098710

申请日：2023-01-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Peng-Hsiu Chen ,  Su-Ming Hsieh ,  Ying-Ren Chen

IPC: H01L27/08 ,  H01L29/66 ,  H01L29/93

CPC classification number: H01L27/0808 ,  H01L29/66174 ,  H01L29/93

Abstract: The invention provides a layout pattern of a semiconductor varactor, which comprises a plurality of varactor units arranged on a substrate, wherein each varactor unit comprises a plurality of fin structures arranged in parallel with each other, a plurality of gate structures arranged in parallel with each other, located on the substrate and spanning the fin structures, and a gate metal layer electrically connected with the plurality of gate structures.

公开(公告)号：US12027600B2

公开(公告)日：2024-07-02

申请号：US18201769

申请日：2023-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai ,  Ching-Wen Hung ,  Chun-Hsien Lin

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/16 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/1606 ,  H01L29/45 ,  H01L29/66045 ,  H01L29/78696

Abstract: A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.