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    RESUMING EXECUTION IN RESPONSE TO A FAILURE
    24.
    发明申请
    RESUMING EXECUTION IN RESPONSE TO A FAILURE 审中-公开
    恢复对失败的响应执行

    公开(公告)号：WO2017074451A1

    公开(公告)日：2017-05-04

    申请号：PCT/US2015/058446

    申请日：2015-10-30

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： IZRAELEVITZ, Joseph ,  KOLLI, Aasheesh ,  KELLY, Terence P. ,  MORREY III, Charles B.

    IPC: G06F11/16 ,  G06F12/02

    CPC classification number: G06F11/1474 ,  G06F21/00 ,  G06F2201/825

    Abstract: A critical section of machine-readable instructions is executed, the critical section including instructions to acquire and release at least one lock. While executing the critical section, information associated with a store instruction that stores data to a persistent memory is logged in a log. In response to an indication of a failure that caused execution of the section to fail to complete, recovery is performed by resuming, using the information in the log, execution of machine-readable instructions of the section starting from a most recent store instruction in the critical section, without executing machine-readable instructions of the critical section prior to the most recent store instruction.

    Abstract translation: 执行机器可读指令的关键部分，该关键部分包括用于获取和释放至少一个锁的指令。 在执行临界区时，与将数据存储到持久性内存的存储指令相关的信息将记录在日志中。 响应于引起执行部分未能完成的故障的指示，通过使用日志中的信息来恢复该部分的机器可读指令的执行，该部分的机器可读指令从第 关键部分，而不在最近的存储指令之前执行关键部分的机器可读指令。

    System and method which perform processing to database
    27.
    发明专利
    System and method which perform processing to database 审中-公开
    执行数据库处理的系统和方法

    公开(公告)号：JP2014038564A

    公开(公告)日：2014-02-27

    申请号：JP2012181880

    申请日：2012-08-20

    Applicant: International Business Maschines Corporation ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

    Inventor： OKAWA MASAHIRO

    IPC: G06F12/00 ,  G06F9/46 ,  G06F9/48

    CPC classification number: H04L67/02 ,  G06F11/1443 ,  G06F11/1471 ,  G06F11/20 ,  G06F11/2023 ,  G06F11/2035 ,  G06F11/2046 ,  G06F2201/80 ,  G06F2201/82 ,  G06F2201/825 ,  H04L69/40

    Abstract: PROBLEM TO BE SOLVED: To continue transaction processing without losing conformity in data, even when a fault occurs in a server before the transaction which processes data is committed in the server among a plurality of servers, in response to a request from a client.SOLUTION: A transaction log storage unit 15 in a client 10 stores an SQL statement issued to a server 20 in association with a transaction ID. When a fault occurs in the server 20, an SQL processing unit 14 in the client 10 sequentially reads SQL statements stored in the transaction log storage unit 15 in association with the transaction ID and reissues an SQL statement using the same transaction ID, and an SQL processing unit 24 in the server 20 processes the reissued SQL statement with the transaction ID, while keeping lock information corresponding to the transaction ID.

    Abstract translation: 要解决的问题：即使在响应于客户端的请求之间的多个服务器之间的服务器中提交处理数据的事务之前的服务器中发生故障时，即使在数据中不继续事务处理也继续进行事务处理。 ：客户端10中的事务日志存储单元15存储与事务ID相关联地发布到服务器20的SQL语句。 当服务器20发生故障时，客户端10中的SQL处理单元14依次读取存储在事务日志存储单元15中的与事务ID相关联的SQL语句，并使用相同的事务ID重新发送SQL语句，并且SQL 服务器20中的处理单元24处理具有事务ID的重新发行的SQL语句，同时保持对应于事务ID的锁定信息。

    DYNAMICALLY CHANGING LOCKSTEP CONFIGURATION
    28.
    发明申请
    DYNAMICALLY CHANGING LOCKSTEP CONFIGURATION 审中-公开
    动态更改LOCKSTEP配置

    公开(公告)号：WO2016127143A1

    公开(公告)日：2016-08-11

    申请号：PCT/US2016/016905

    申请日：2016-02-06

    Applicant: INTEL CORPORATION

    Inventor： DAS, Debaleena ,  HUANG, George H ,  LING, Jing ,  DAFTARI, Reza E ,  GANESAN, Meera

    IPC: G06F11/16

    CPC classification number: G06F11/1662 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/0647 ,  G06F3/0683 ,  G06F11/00 ,  G06F11/2094 ,  G06F2201/825

    Abstract: Memory subsystem error management enables dynamically changing lockstep partnerships. A memory subsystem has a lockstep partnership relationship between a first memory portion and a second memory portion to spread error correction over the pair of memory resources. The lockstep partnership can be preconfigured. In response to detecting a hard error in the lockstep partnership, the memory subsystem can cancel or reverse the lockstep partnership between the first memory portion and the second memory portion and create or set a new lockstep partnership. The detected error can be a second hard error in the lockstep partnership. The memory subsystem can create new lockstep partnerships between the first memory portion and a third memory portion as lockstep partners and between the second memory portion and a fourth memory portion as lockstep partners. The memory subsystem can also be configured to change the granularity of the lockstep partnership when changing partnerships.

    Abstract translation: 内存子系统错误管理可实现动态更改的锁步合作伙伴关系。 存储器子系统具有在第一存储器部分和第二存储器部分之间的锁步合作关系，以在所述一对存储器资源上扩展纠错。 锁定合作伙伴关系可以预先配置。 响应于检测锁步伙伴关系中的硬错误，存储器子系统可以取消或反转第一存储器部分和第二存储器部分之间的锁步合作关系，并创建或设置新的锁步伙伴关系。 检测到的错误可能是锁步伙伴关系中的第二个硬错误。 存储器子系统可以在第一存储器部分和第三存储器部分之间创建新的锁步合作关系，作为锁步伙伴，并且在第二存储器部分和作为锁步伙伴的第四存储器部分之间。 内存子系统也可以配置为在更改合作伙伴关系时更改锁步伙伴关系的粒度。

    SYNCHRONIZATION IN A COMPUTING DEVICE
    29.
    发明申请
    SYNCHRONIZATION IN A COMPUTING DEVICE 审中-公开
    计算设备中的同步

    公开(公告)号：WO2016094030A1

    公开(公告)日：2016-06-16

    申请号：PCT/US2015/060610

    申请日：2015-11-13

    Applicant: INTEL CORPORATION

    Inventor： WU, Keqiang ,  LU, Jiwei ,  LEE, Yong-Fong

    IPC: G06F13/16 ,  G06F13/14

    CPC classification number: G06F9/30065 ,  G06F8/52 ,  G06F8/70 ,  G06F9/30087 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/3466 ,  G06F2201/81 ,  G06F2201/825 ,  G06F2201/865 ,  G06F2201/88

    Abstract: One embodiment provides an apparatus. The apparatus includes a processor, a chipset, a memory to store a process, and logic. The processor includes one or more core(s) and is to execute the process. The logic is to acquire performance monitoring data in response to a platform processor utilization parameter (PUP) greater than a detection utilization threshold (UT), identify a spin loop based, at least in part, on at least one of a detected hot function and/or a detected hot loop, modify the identified spin loop using binary translation to create a modified process portion, and implement redirection from the identified spin loop to the modified process portion.

    Abstract translation: 一个实施例提供了一种装置。 该装置包括处理器，芯片组，用于存储处理的存储器和逻辑。 处理器包括一个或多个核心，并且是执行该过程。 逻辑是响应于大于检测利用阈值（UT）的平台处理器利用参数（PUP）来获取性能监视数据，至少部分地基于检测到的热功能和 /或检测到的热循环，使用二进制转换修改所识别的自旋循环，以创建经修改的处理部分，并且实现从所识别的旋转循环到修改的处理部分的重定向。

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