公开(公告)号：US20130023088A1

公开(公告)日：2013-01-24

申请号：US13629931

申请日：2012-09-28

Applicant: Ravi K. Nalla ,  Mathew Manusharow ,  Pramod Malatkar

Inventor： Ravi K. Nalla ,  Mathew Manusharow ,  Pramod Malatkar

IPC: H01L21/50

CPC classification number: H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/93 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/21 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/22 ,  H01L2224/2201 ,  H01L2224/221 ,  H01L2224/24011 ,  H01L2224/24146 ,  H01L2224/251 ,  H01L2224/25105 ,  H01L2224/2518 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/821 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/93 ,  H01L2225/06524 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/82 ,  H01L2221/68304 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include a die embedded in a coreless substrate, wherein a mold compound surrounds the die, and wherein the die comprises TSV connections on a first side and C4 pads on a second side of the die, a dielectric material on a first side and on a second side of the mold compound; and interconnect structures coupled to the C4 pads and to the TSV pads. Embodiments further include forming packaging structures wherein multiple dies are fully embedded within a BBUL package without PoP lands.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括嵌入在无芯基板中的模具，其中模具化合物围绕模头，并且其中模具包括在第一侧上的TSV连接和在模具的第二侧上的C4焊盘，在第一侧上的电介质材料， 在模具化合物的第二面上; 以及耦合到C4焊盘和TSV焊盘的互连结构。 实施例还包括形成其中多个管芯完全嵌入在不具有PoP焊盘的BBUL封装内的封装结构。

公开(公告)号：US20120288999A1

公开(公告)日：2012-11-15

申请号：US13554605

申请日：2012-07-20

Applicant: Mayumi NAKASATO ,  Kouichi Saitou

Inventor： Mayumi NAKASATO ,  Kouichi Saitou

IPC: H01L21/78

CPC classification number: H01L23/3114 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2221/68336 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/2101 ,  H01L2224/215 ,  H01L2224/2201 ,  H01L2224/221 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor module includes: bonding a semiconductor substrate onto a first insulating resin layer; dicing the semiconductor substrate into a plurality of individual semiconductor devices; widening the spacings between the adjacent semiconductor devices by expanding the first insulating resin layer in a biaxially stretched manner; fixing the plurality of semiconductor devices to a flat sheet, with a second insulating resin layer held between the plurality of semiconductor devices and the flat sheet, and removing the first insulating resin layer; stacking the plurality of semiconductor devices, a third insulating resin layer, and a metallic plate, in this order, so as to form a laminated body having electrodes by which to electrically connect the device electrodes to the metallic plate; forming a wiring layer by selectively removing the metallic plate and forming a plurality of semiconductor modules; and separating the semiconductor modules into individual units.

Abstract translation: 一种制造半导体模块的方法包括：将半导体衬底接合到第一绝缘树脂层上; 将半导体衬底切割成多个单独的半导体器件; 通过以双向拉伸方式膨胀第一绝缘树脂层来加宽相邻半导体器件之间的间距; 将多个半导体器件固定到平板上，其中第二绝缘树脂层保持在多个半导体器件和平片之间，并且去除第一绝缘树脂层; 依次层叠多个半导体器件，第三绝缘树脂层和金属板，以形成具有电极的层叠体，用于将器件电极与金属板电连接; 通过选择性地去除所述金属板并形成多个半导体模块来形成布线层; 并将半导体模块分离成单独的单元。

公开(公告)号：US11749657B2

公开(公告)日：2023-09-05

申请号：US17476291

申请日：2021-09-15

Applicant: SJ Semiconductor (Jiangyin) Corporation

Inventor： Yenheng Chen ,  Chengchung Lin

IPC: H01L25/16 ,  H01L23/00

CPC classification number: H01L25/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L2224/2201 ,  H01L2224/221 ,  H01L2224/244 ,  H01L2224/24145 ,  H01L2224/24265 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73217 ,  H01L2224/73259

Abstract: The present disclosure provides a fan-out chip packaging structure and a method to fabricate the fan-out chip package. The fan-out chip packaging structure includes a first redistribution layer, a second redistribution layer, metal connecting posts, a semiconductor chip, a first packaging layer, a stacked chip package, a passive element, a filling layer, a metal bumps, and a second packaging layer. By means of the present disclosure, various chips having different functions can be integrated into one package structure, thereby improving the integration level of the fan-out packaging structure. By means of the first redistribution layer, the second redistribution layer, and the metal connecting posts, a three-dimensional vertically stacked package is achieved. In this way, the integration level of the packaging structure can be effectively improved, and the conduction path can be effectively shortened, thereby reducing power consumption, increasing the transmission speed, and increasing the data processing capacity.

公开(公告)号：US08535980B2

公开(公告)日：2013-09-17

申请号：US12977697

申请日：2010-12-23

Applicant: Puay Gek Chua ,  Yonggang Jin

Inventor： Puay Gek Chua ,  Yonggang Jin

IPC: H01L21/00

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/21 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/22 ,  H01L2224/2201 ,  H01L2224/2205 ,  H01L2224/221 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  Y10T408/566 ,  H01L2924/014 ,  H01L2924/00

Abstract: A process for manufacturing semiconductor packages is provided, that includes drilling blind apertures in a reconstituted wafer, adhering a dry film resist on the wafer over the apertures, and patterning the film to expose a space around each of the apertures. The apertures and spaces are then filled with conductive paste by wiping a quantity of the paste across a surface of the film so that paste is forced into the spaces and apertures. The spaces around the apertures define contact pads whose thickness is constrained by the thickness of the film, preferably to about 10 μm or less. To prevent paste from trapping air pockets in the apertures, the wiping process can be performed in a chamber from which much or all of the air has been evacuated. After curing the paste, the wafer is thinned from the back to expose the cured paste in the apertures.

Abstract translation: 提供了一种用于制造半导体封装的工艺，其包括在重构的晶片中钻孔盲孔，将覆盖在晶片上的干膜抗蚀剂粘附在孔上，以及图案化膜以暴露每个孔周围的空间。 然后通过在胶片的表面上擦拭一定量的糊料，将导电浆料填充到孔和空间中，使得糊料被迫进入空间和孔。 孔周围的空间限定了其厚度受薄膜厚度限制的接触垫，优选为约10μm或更小。 为了防止糊料在孔中捕获气穴，擦拭过程可以在空气中进行大量或全部空气的​​室中进行。 在固化糊料之后，晶片从后面变薄以露出孔中的固化糊料。

公开(公告)号：US20120320549A1

公开(公告)日：2012-12-20

申请号：US13515012

申请日：2010-12-17

Applicant: Thomas Gottwald ,  Alexander Neumann

Inventor： Thomas Gottwald ,  Alexander Neumann

IPC: H05K7/00 ,  H05K3/46 ,  H01L23/48

CPC classification number: H05K1/186 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2221/6835 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/2201 ,  H01L2224/221 ,  H01L2224/224 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/9202 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/01061 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H05K1/189 ,  H05K3/205 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/462 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/10977 ,  H05K2203/063 ,  H05K2203/1469 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/83851

Abstract: The present invention relates to a method for producing a conductor structural element, comprising providing a rigid substrate, electrodepositing a copper coating on the rigid substrate, applying a conductor pattern structure to the copper coating, then possibly mounting components, laminating the substrate with at least one electrically insulating layer, detaching the rigid substrate, at least partially removing the remaining copper coating of the rigid substrate in such a way that the conductor pattern structure is exposed.

Abstract translation: 导体结构元件的制造方法技术领域本发明涉及一种导体结构元件的制造方法，其特征在于，提供刚性基板，在所述刚性基板上电沉积铜涂层，将铜导体图案结构施加到所述铜涂层上，然后可能安装部件，至少层叠所述基板 一个电绝缘层，分离刚性基板，至少部分地去除刚性基板的剩余的铜涂层，使得暴露导体图案结构。

公开(公告)号：US20120161332A1

公开(公告)日：2012-06-28

申请号：US12977697

申请日：2010-12-23

Applicant: Puay Gek Chua ,  Yonggang Jin

Inventor： Puay Gek Chua ,  Yonggang Jin

IPC: H01L23/538 ,  H01L21/60 ,  H01L21/768

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/21 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/22 ,  H01L2224/2201 ,  H01L2224/2205 ,  H01L2224/221 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  Y10T408/566 ,  H01L2924/014 ,  H01L2924/00

Abstract: A process for manufacturing semiconductor packages is provided, that includes drilling blind apertures in a reconstituted wafer, adhering a dry film resist on the wafer over the apertures, and patterning the film to expose a space around each of the apertures. The apertures and spaces are then filled with conductive paste by wiping a quantity of the paste across a surface of the film so that paste is forced into the spaces and apertures. The spaces around the apertures define contact pads whose thickness is constrained by the thickness of the film, preferably to about 10 μm or less. To prevent paste from trapping air pockets in the apertures, the wiping process can be performed in a chamber from which much or all of the air has been evacuated. After curing the paste, the wafer is thinned from the back to expose the cured paste in the apertures.

Abstract translation: 提供了一种用于制造半导体封装的工艺，其包括在重构的晶片中钻孔盲孔，将覆盖在晶片上的干膜抗蚀剂粘附在孔上，以及图案化膜以暴露每个孔周围的空间。 然后通过在胶片的表面上擦拭一定量的糊料，将导电浆料填充到孔和空间中，使得糊料被迫进入空间和孔。 孔周围的空间限定了其厚度受薄膜厚度限制的接触垫，优选为约10μm或更小。 为了防止糊料在孔中捕获气穴，擦拭过程可以在空气中进行大量或全部空气的​​室中进行。 在固化糊料之后，晶片从后面变薄以露出孔中的固化糊料。

公开(公告)号：US20110278733A1

公开(公告)日：2011-11-17

申请号：US13103191

申请日：2011-05-09

Applicant: Eric Saugier

Inventor： Eric Saugier

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/563 ,  H01L21/568 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2201 ,  H01L2224/221 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2224/9202 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2224/81 ,  H01L2924/00

Abstract: A semiconductor device includes a first wafer having at least one first integrated-circuit chip and a first support layer surrounding the first integrated circuit chip. A first electrical-connection layer is placed on a frontside of the first wafer and includes a first electrical-connection network. A second wafer is placed on a frontside of the first electrical-connection layer. The second wafer includes at least one second integrated-circuit chip and a second support layer surrounding the second integrate circuit chip. The second integrated circuit chip has an active side facing the first electrical-connection layer, and one or more through-holes filled with a conductor forming electrical-connection vias. A second electrical-connection layer is placed on the backside of the second wafer and includes a second electrical-connection network.

Abstract translation: 半导体器件包括具有至少一个第一集成电路芯片的第一晶片和围绕第一集成电路芯片的第一支撑层。 第一电连接层被放置在第一晶片的前侧并且包括第一电连接网络。 第二晶片放置在第一电连接层的前侧。 第二晶片包括至少一个第二集成电路芯片和围绕第二集成电路芯片的第二支撑层。 第二集成电路芯片具有面向第一电连接层的有源侧和填充有形成电连接通孔的导体的一个或多个通孔。 第二电连接层被放置在第二晶片的背面并且包括第二电连接网络。

公开(公告)号：US20240030095A1

公开(公告)日：2024-01-25

申请号：US18473775

申请日：2023-09-25

Applicant: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft

Inventor： Mikael Andreas Tuominen ,  Seok Kim Tay ,  Johannes Stahr ,  Andreas Zluc ,  Timo Schwarz ,  Gerald Weidinger ,  Mario Schober

IPC: H01L23/373 ,  H01L23/492 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/3737 ,  H01L23/492 ,  H01L24/20 ,  H01L24/19 ,  H01L21/56 ,  H01L2224/21 ,  H01L2224/2201 ,  H01L2224/19

Abstract: An electronic package having a base structure; a layer stack formed over the base structure; and a component embedded at least partially within the base structure and/or within the layer stack. The layer stack has a decoupling layer structure, the decoupling layer structure with a decoupling material having a Young Modulus being smaller than 1 GPa.

公开(公告)号：US11824033B2

公开(公告)日：2023-11-21

申请号：US18149342

申请日：2023-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyoyoung Jung ,  Jinsu Kim ,  Hyunsuk Yang ,  Kiju Lee ,  Hoyeon Jo ,  Ikkyu Jin

IPC: H01L23/00 ,  H01L25/16

CPC classification number: H01L24/20 ,  H01L24/13 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/13005 ,  H01L2224/13024 ,  H01L2224/2105 ,  H01L2224/2201 ,  H01L2224/2205 ,  H01L2224/24155 ,  H01L2224/24265 ,  H01L2224/2518 ,  H01L2224/25171 ,  H01L2224/73217 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1441 ,  H01L2924/1443 ,  H01L2924/19041 ,  H01L2924/19104

Abstract: A semiconductor package including a core substrate, a semiconductor chip in the core substrate and having chip pads, a redistribution wiring layer covering a lower surface of the core substrate and including redistribution wirings electrically connected to the chip pads and a pair of capacitor pads exposed from an outer surface of the redistribution wiring layer, conductive pastes on the capacitor pads, respectively, and a capacitor via the conductive pastes and having first and second outer electrodes on the capacitor pads, respectively, may be provided. Each of the capacitor pads includes a pad pattern exposed from the outer surface of the redistribution wiring layer, and at least one via pattern at a lower portion of the pad pattern and electrically connected to at least one of the redistribution wirings. The via pattern is eccentric by a distance from a center line of the pad pattern.

公开(公告)号：US09456500B2

公开(公告)日：2016-09-27

申请号：US13515012

申请日：2010-12-17

Applicant: Thomas Gottwald ,  Alexander Neumann

Inventor： Thomas Gottwald ,  Alexander Neumann

IPC: H05K3/30 ,  H05K1/18 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H05K3/20 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K1/186 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2221/6835 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/2201 ,  H01L2224/221 ,  H01L2224/224 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/9202 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/01061 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H05K1/189 ,  H05K3/205 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/462 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/10977 ,  H05K2203/063 ,  H05K2203/1469 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/83851

Abstract: The present invention relates to a method for producing a conductor structural element, comprising providing a rigid substrate, electrodepositing a copper coating on the rigid substrate, applying a conductor pattern structure to the copper coating, then possibly mounting components, laminating the substrate with at least one electrically insulating layer, detaching the rigid substrate, at least partially removing the remaining copper coating of the rigid substrate in such a way that the conductor pattern structure is exposed.

Abstract translation: 导体结构元件的制造方法技术领域本发明涉及一种导体结构元件的制造方法，其特征在于，提供刚性基板，在所述刚性基板上电沉积铜涂层，将铜导体图案结构施加到所述铜涂层上，然后可能安装部件，至少层叠所述基板 一个电绝缘层，分离刚性基板，至少部分地去除刚性基板的剩余的铜涂层，使得暴露导体图案结构。