公开(公告)号：EP1841298A3

公开(公告)日：2008-05-07

申请号：EP07110136.4

申请日：2005-02-14

Applicant: MOLEX INCORPORATED

Inventor： Regnier, Kent, E. ,  Brunker, David, L. ,  Ogbuokiri, Martin, U.

IPC: H05K1/11 ,  H05K1/02 ,  H01L23/64 ,  H01L23/66 ,  H01R24/00 ,  H01R12/16

CPC classification number: H05K1/0251 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09609 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/10189 ,  H01L2924/00

Abstract: A circuit board (600) design is disclosed that is useful in high speed differential signal applications uses a circuit trace exit structure (620) and optionally a via arrangement. The circuit trace exit structure involves the exit portions (620) of the circuit traces (550) of the differential signal vias (609) to follow a path where the traces then meet with and join to the transmission line portions (552,612) of the conductive traces (550). In the via arrangement, sets of differential signal pair vias (551,609) and an associated ground (593a) are arranged adjacent to each other in a repeating pattern. The differential signal vias of each pair (591) are spaced closer to their associated ground via (593a) than the spacing between the adjacent differential signal pair associated ground (593b) so that differential signal vias exhibit a preference for electrically coupling to their associated ground vias.

Abstract translation: 公开了一种在高速差分信号应用中使用电路走线出口结构（620）和可选的通孔装置的电路板（600）设计。 电路走线出口结构涉及差分信号通孔（609）的电路迹线（550）的出口部分（620），以跟随路径，其中迹线然后与导体的传输线部分（552,612）相接并连接 痕迹（550）。 在通孔布置中，差分信号对通孔（551,609）和相关联的接地（593a）的组以重复图案彼此相邻布置。 每对（591）的差分信号通孔（593a）比相邻的差分信号对相关联的接地（593b）之间的间隔更靠近其相关联的接地，使得差分信号通孔表现出对它们的相关接地电耦合的偏好 孔。

公开(公告)号：EP1878326A2

公开(公告)日：2008-01-16

申请号：EP06740704.9

申请日：2006-04-05

Applicant: FCI

Inventor： MINICH, Steven ,  SMITH, Stephen, B. ,  MORLION, Danny

IPC: H05K1/00

CPC classification number: H01R12/737 ,  H01R12/716 ,  H01R12/724 ,  H01R13/6585 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/114 ,  H05K1/115 ,  H05K1/14 ,  H05K3/308 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09627 ,  H05K2201/10189 ,  H05K2201/1059 ,  H05K2201/10659

Abstract: An orthogonal backplane connector systems having midplane footprints that provide for continuity of impedance and signal integrity through the midplane and allow for the same connector to be coupled to either side of the midplane. This design creates an orthogonal interconnect without taking up unnecessary PCB real estate. The midplane circuit board may include a first differential signal pair of electrically conductive vias disposed in a first direction, and a second differential signal pair of electrically conductive vias disposed in a second direction that is generally orthogonal to the first direction.

公开(公告)号：EP1813001A4

公开(公告)日：2007-12-12

申请号：EP05812154

申请日：2005-10-17

Applicant: FRAMATOME CONNECTORS INT

Inventor： MINICH STEVEN

IPC: H05K1/14 ,  H01R12/04 ,  H01R29/00 ,  H05K7/14

CPC classification number: H05K1/144 ,  H01R12/585 ,  H05K3/308 ,  H05K2201/044 ,  H05K2201/096 ,  H05K2201/10189 ,  H05K2201/1059

Abstract: A mid-plane is disclosed. The mid-plane includes a first printed circuit board having a plurality of plated vias adapted to receive tails attached to a first connector and having a plurality of unplated clearance holes adapted to receive tails attached to a second connector. The second printed circuit board has a plurality of plated vias adapted to receive tails attached to the second connector and has a plurality of unplated clearance adapted to receive tails attached to the first connector.

公开(公告)号：EP1841298A2

公开(公告)日：2007-10-03

申请号：EP07110136.4

申请日：2005-02-14

Applicant: MOLEX INCORPORATED

Inventor： Regnier, Kent, E. ,  Brunker, David, L. ,  Ogbuokiri, Martin, U.

IPC: H05K1/11 ,  H05K1/02 ,  H01L23/64 ,  H01L23/66 ,  H01R24/00 ,  H01R12/16

CPC classification number: H05K1/0251 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09609 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/10189 ,  H01L2924/00

Abstract: A circuit board (600) design is disclosed that is useful in high speed differential signal applications uses a circuit trace exit structure (620) and optionally a via arrangement. The circuit trace exit structure involves the exit portions (620) of the circuit traces (550) of the differential signal vias (609) to follow a path where the traces then meet with and join to the transmission line portions (552,612) of the conductive traces (550). In the via arrangement, sets of differential signal pair vias (551,609) and an associated ground (593a) are arranged adjacent to each other in a repeating pattern. The differential signal vias of each pair (591) are spaced closer to their associated ground via (593a) than the spacing between the adjacent differential signal pair associated ground (593b) so that differential signal vias exhibit a preference for electrically coupling to their associated ground vias.

公开(公告)号：EP1733568A1

公开(公告)日：2006-12-20

申请号：EP05724516.9

申请日：2005-03-02

Applicant: ADC Telecommunications, Inc.

Inventor： COFFEY, Joseph, Christopher ,  SCHMIDT, John, D. ,  OGREN, Bruce, C. ,  PETERSON, Karl, J.

IPC: H04Q1/14

CPC classification number: H04Q1/03 ,  H04Q1/13 ,  H04Q1/146 ,  H04Q1/155 ,  H04Q2201/02 ,  H04Q2201/04 ,  H04Q2201/10 ,  H04Q2201/12 ,  H04Q2201/802 ,  H05K1/14 ,  H05K2201/044 ,  H05K2201/10189 ,  Y10T29/49117 ,  Y10T29/49174 ,  Y10T29/49194 ,  Y10T29/49195

Abstract: A patch panel includes a back plane having front mounted pairs of termination locations, and an interconnect location electrically connected to each pair of termination locations. The termination locations connect to two patch cords. The interconnect location defines an access device for selectively accessing the termination locations. An interconnect module interfaces with the interconnect location. The module can include test access, power over Ethernet, or circuit protection features.

公开(公告)号：EP1544948A3

公开(公告)日：2006-08-02

申请号：EP04029720.2

申请日：2004-12-15

Applicant: Palo Alto Research Center Incorporated

Inventor： Vanschuylenbergh, Koenraad F. ,  Volkel, Armin R. ,  Distefano, Thomas H. ,  Rosa, Michel A. ,  Fork, David K. ,  Chow, Eugene M. ,  Lean, Meng H.

IPC: H01R12/04

CPC classification number: H01R12/78 ,  H05K1/147 ,  H05K3/323 ,  H05K3/361 ,  H05K3/365 ,  H05K2201/044 ,  H05K2201/09845

Abstract: A data transmission interconnect assembly (e.g., a router) capable of transmission speeds in excess of 40Gbps in which a line-card is detachably coupled to a backplane using flexible flat cables that are bent to provide a continuous, smooth curve between the connected boards, and connected by a connection apparatus that employs cable-to-cable interface members that are transparent to the transmitted signal waves. Microspring contact structures are formed on the cables, or on a contact structure pressed against the cables, to provide interface arrangements that are smaller than a wavelength of the transmitted signal. A connector apparatus uses a cam mechanism to align the cables, and then to press a contact structure, having micro spring interface members formed thereon, against the cables. An alterative contact structure uses anisotropic conductive film.

公开(公告)号：EP1629391A2

公开(公告)日：2006-03-01

申请号：EP04785700.8

申请日：2004-05-20

Applicant: INTEL CORPORATION

Inventor： BENHAM, John ,  CRITCHLOW, John ,  LIANG, Tao

IPC: G06F13/40

CPC classification number: G06F13/4086 ,  H01P5/185 ,  H05K1/0239 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/10189

Abstract: A compact electromagnetic coupler for use with digital transmission system is described. In one embodiment, the apparatus includes a first transmission structure, including a portion having a geometry. A second transmission structure having the geometry and positioned proximate the portion of the first transmission line structure having the geometry to form a compact electromagnetic coupler with the first transmission structure a geometry of the electromagnetic coupler to enable placement within a footprint of a standard card connector. The compact electromagnetic coupler so formed enables reconstruction of the logical state and timing of a signal transmitted along the first transmission structure.

公开(公告)号：EP1550875A1

公开(公告)日：2005-07-06

申请号：EP04030708.4

申请日：2004-12-23

Applicant: TERADYNE, INC.

Inventor： Yevmenenko, Yan

IPC: G01R1/04 ,  H05K7/14 ,  G06K7/00

CPC classification number: H05K1/0266 ,  H05K1/14 ,  H05K7/1424 ,  H05K2201/044 ,  H05K2201/10151 ,  H05K2203/168

Abstract: A control (64,66) system indicates whether a module (36) should be inserted into a module holder (30). The control system includes a sensor (60) which is configured to attach to one of a module and the module holder. The sensor is further configured to (i) read an identifier of an element (58) attached to the other of the module and the module holder when the module begins insertion into the module holder and (ii) provide a sensor signal in response to reading the identifier. The sensor signal denotes the identifier. The control system further includes a controller which couples to the sensor. The controller is configured to receive the sensor signal from the sensor and output a control signal (66) based on the sensor signal. The control signal indicates whether the module is authorized to substantially insert into the module holder.

Abstract translation: 控制（64,66）系统指示模块（36）是否应插入模块支架（30）中。 控制系统包括被配置为附接到模块和模块保持器之一的传感器（60）。 所述传感器进一步配置为：（i）当所述模块开始插入所述模块保持器时，（i）响应于读取提供传感器信号，读取连接到所述模块中的另一个和所述模块保持器的元件（58）的标识符 标识符。 传感器信号表示标识符。 控制系统还包括耦合到传感器的控制器。 控制器被配置为从传感器接收传感器信号并且基于传感器信号输出控制信号（66）。 控制信号指示模块是否被授权基本插入模块支架。

公开(公告)号：EP1422717A1

公开(公告)日：2004-05-26

申请号：EP02026015.4

申请日：2002-11-21

Applicant: Infineon Technologies AG

Inventor： Kuzmenka, Maksim

IPC: G11C5/00

CPC classification number: H05K1/147 ,  G11C5/00 ,  H05K1/148 ,  H05K3/222 ,  H05K2201/044

Abstract: A memory system has a circuit board (100) provided with a first slot connector (104) into which a first memory module (114) is inserted. A second slot connector (106) is provided into which a second memory module (116) is inserted. The first and the second memory modules (114, 116) are connected via a flexible bridge (138). The flexible bridge extends from respective ends of the memory modules opposite to that ends thereof which are inserted into the connector slots. The flexible bridge (138) provides a signal bus between the memory modules (114, 116).

Abstract translation: 存储器系统具有设置有第一存储器模块（114）插入其中的第一槽连接器（104）的电路板（100）。 提供第二插槽连接器（106），第二存储器模块（116）插入到该第二插槽连接器（106）中。 第一和第二存储器模块（114,116）经由柔性桥（138）连接。 柔性桥从相对于插入连接器槽的其端部的存储器模块的相应端部延伸。 柔性桥（138）在存储器模块（114,116）之间提供信号总线。

公开(公告)号：EP0940850B1

公开(公告)日：2003-08-13

申请号：EP99102664.2

申请日：1999-02-12

Applicant: Infineon Technologies AG

Inventor： Loeffler, Steffen

IPC: H01L25/065 ,  H05K1/14

CPC classification number: H05K1/14 ,  G11C5/04 ,  G11C5/063 ,  H05K1/0246 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10545 ,  H05K2201/10689 ,  H05K2203/1572