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    POWER PACKAGE WITH COPPER PLATING AND MOLDING STRUCTURE
    375.
    发明公开
    POWER PACKAGE WITH COPPER PLATING AND MOLDING STRUCTURE 审中-公开

    公开(公告)号：EP4310908A3

    公开(公告)日：2024-03-06

    申请号：EP23186436.4

    申请日：2023-07-19

    Applicant: STMicroelectronics Pte Ltd.

    Inventor： RENARD, Loic Pierre Louis

    IPC: H01L23/495 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/057 ,  H01L23/492

    Abstract: The present disclosure is directed to a power package with copper plating terminals. The power package includes at least two terminals coupled to a semiconductor die. An area of a first terminal is greater than an area of a second terminal. The first and second terminals extend to a first and second conductive layers in a backside of the package. A third conductive layer is coupled to a backside surface of the die that is coplanar with the first and second conductive layers. The terminals and conductive layers are copper plating. A first molding compound covers the die and terminals, while a second molding compound fills distances between the die and the extensions of the terminals. The copper plating and the molding compounds enhance the performance of the packaged device in a high-power circuit. In addition, robustness of the package is enhanced compared with conventional packages including wire bonding.

    MONOLITHIC CHARGE COUPLED FIELD EFFECT RECTIFIER EMBEDDED IN A CHARGE COUPLED FIELD EFFECT TRANSISTOR
    376.
    发明公开
    MONOLITHIC CHARGE COUPLED FIELD EFFECT RECTIFIER EMBEDDED IN A CHARGE COUPLED FIELD EFFECT TRANSISTOR 审中-公开

    公开(公告)号：EP3902015A1

    公开(公告)日：2021-10-27

    申请号：EP21169556.4

    申请日：2021-04-21

    Applicant: STMicroelectronics Pte Ltd.

    Inventor： LEE, Shin Phay ,  NGWAN, Voon Cheng ,  CASTORINA, Maurizio Gabriele

    IPC: H01L29/78 ,  H01L27/07

    Abstract: An integrated circuit includes a MOSFET device and a monolithic diode device, wherein the monolithic diode device is electrically connected in parallel with a body diode of the MOSFET device. The monolithic diode device is configured so that a forward voltage drop Vf D2 of the monolithic diode device is less than a forward voltage drop Vf D1 of the body diode of the MOSFET device. The forward voltage drop Vf D2 is process tunable by controlling a gate oxide thickness, a channel length and body doping concentration level. The tunability of the forward voltage drop Vf D2 advantageously permits design of the integrated circuit to suit a wide range of applications according to requirements of switching speed and efficiency.

    MEMS THIN MEMBRANE WITH STRESS STRUCTURE
    377.
    发明公开
    MEMS THIN MEMBRANE WITH STRESS STRUCTURE 审中-公开

    公开(公告)号：EP3851822A1

    公开(公告)日：2021-07-21

    申请号：EP21150139.0

    申请日：2021-01-05

    Applicant: STMicroelectronics Pte Ltd.

    Inventor： SHANKAR, Ravi ,  LOH, Tien Choy ,  VENKATESAN, Ananya

    IPC: G01L9/00

    Abstract: A blind opening is formed in a bottom surface of a semiconductor substrate to define a thin membrane suspended from a substrate frame. The thin membrane has a topside surface and a bottomside surface. A stress structure is mounted to one of the topside surface or bottomside surface of the thin membrane. The stress structure induces a bending of the thin membrane which defines a normal state for the thin membrane. Piezoresistors are supported by the thin membrane. In response to an applied pressure, the thin membrane is bent away from the normal state and a change in resistance of the piezoresistors is indicative of the applied pressure.

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