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公开(公告)号:JP2004070959A
公开(公告)日:2004-03-04
申请号:JP2003288282
申请日:2003-08-06
Applicant: Apple Computer Inc , アップル コンピュータ, インコーポレイテッド
Inventor: KIDA YASUO , IWASAKI MICHI , HARA KEISUKE , TAKANO TAKUMI
CPC classification number: G06F17/276 , G06F17/2223 , G06F17/2863
Abstract: PROBLEM TO BE SOLVED: To solve a problem that a grammatical and a semantic analysis used for an existing conversion engine of Japanese do not select a right Chinese character. SOLUTION: A method, device, system, and a signal-bearing medium which convert input data such as a speech or phonetic characters into a text by finding documents similar to input data and using the similar documents to create a customized dictionary including a weighted list of words found in a similar document are provided. The words that are weighted higher may have a higher probability being used in the input data, so words in the converted text are selected based on the weighted list. A vector space model can be used to search for the similar document. COPYRIGHT: (C)2004,JPO
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公开(公告)号:JP2002314566A
公开(公告)日:2002-10-25
申请号:JP2002053713
申请日:2002-02-28
Applicant: APPLE COMPUTER
Inventor: OPRESCU FLORIN
IPC: G06F13/368 , G06F13/00 , G06F13/36 , G06F13/362 , G06F13/40 , G06F13/42 , G06F15/16 , G06F15/173 , G06F15/177 , H04L12/40 , H04L12/44 , H04L12/56 , H04L12/64
Abstract: PROBLEM TO BE SOLVED: To provide a system where an arbitrary assembly of nodes on a system bus have been resolved into an acyclic directed graph and communication between the nodes is established. SOLUTION: The method performs the constituent bus access arbitration system, the preferential bus access arbitration system, the token passing bus arbitration system, and the preemptive bus initialization mechanism or the like.
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公开(公告)号:JP2002314565A
公开(公告)日:2002-10-25
申请号:JP2002053699
申请日:2002-02-28
Applicant: APPLE COMPUTER
Inventor: OPRESCU FLORIN
IPC: G06F13/368 , G06F13/00 , G06F13/36 , G06F13/362 , G06F13/40 , G06F13/42 , G06F15/16 , G06F15/173 , G06F15/177 , H04L12/40 , H04L12/44 , H04L12/56 , H04L12/64
Abstract: PROBLEM TO BE SOLVED: To provide a system where an arbitrary assembly of nodes on a system bus have been resolved into an acyclic directed graph and communication between the nodes is established. SOLUTION: The method performs the constituent bus access arbitration system, the preferential bus access arbitration system, the token passing bus arbitration system, and the preemptive bus initialization mechanism or the like.
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公开(公告)号:JPH08235102A
公开(公告)日:1996-09-13
申请号:JP29867995
申请日:1995-11-16
Applicant: APPLE COMPUTER
IPC: G06F13/28
Abstract: PROBLEM TO BE SOLVED: To provide a system and method for designating a substitute data stream and memory address space during a DMA transferring period. SOLUTION: The key field of a channel command is constituted so that the use of a substitute data port instead of a standard data stream can be designated. The data port can be formed in an unaddressed substitute data stream, such as the control/status steam, etc., or in another addressable space, such as the system memory, input-output address space, channel register space, etc. When a second addressable space is designated, another channel register is used for storing secondary addresses.
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公开(公告)号:JPH07245944A
公开(公告)日:1995-09-19
申请号:JP31421992
申请日:1992-10-30
Applicant: APPLE COMPUTER
Inventor: SUTEIIBUN JIEI YANGU
Abstract: PURPOSE: To enhance the output efficiency for a load variable over a wide range by compensating for the fluctuation of load current through regulation of the duty cycle of a square wave generator and turning the square wave generator off completely over a significantly large part of the operating time of a power supply when the current demand level is low. CONSTITUTION: Upon receiving an output signal from a programmable reference generator 45 and an operation mode signal from a controller 50, a switching regulator 15 outputs a square wave to the primary coil 22 of a transformer 20 which produces a DC output voltage through the secondary coil thereof. In full-on constant voltage mode, a constant voltage output is sustained by varying the duty cycle of the square wave continuously with a feedback signal generated from a reference voltage generator 45. The controller 50 monitors the load demand level and when it drops below a specified level, a transition signal to burst mode is delivered and the switching regulator 15 is paused except the charging interval of capacitors 61, 63.
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公开(公告)号:JPH06309466A
公开(公告)日:1994-11-04
申请号:JP13384093
申请日:1993-05-12
Applicant: APPLE COMPUTER
Inventor: KIYARII KURAAKU
Abstract: PURPOSE: To obtain the device and method for effectively generating and operating a graphical image to be displayed on an output device of a computer. CONSTITUTION: All graphical images are maintained as single base geometry on which every possible geometric operation is imposed. Simplified geometry is called a shape and shapes are put together to obtain an object called a picture. Geometric operation is done at any time for geometry in a local space and those operation results are drawn whatever display device is used in a layer for a hierarchical output method. A cache is maintained for geometry calculation, so the calculation needs to be done only once irrelevantly to the resolution of an output display and geometric information is never lost as a result of a bit map process.
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公开(公告)号:JPH06266900A
公开(公告)日:1994-09-22
申请号:JP13757592
申请日:1992-05-01
Applicant: APPLE COMPUTER
Inventor: DEBUITSUDO FUENUITSUKU
Abstract: PURPOSE: To correctly recognize a character space, to correct it and to output an array. CONSTITUTION: This device stores every input character, compares a last entry in each buffer (memory 16) with a known word dictionary, copies a last entry which coincides with a word to a new buffer, places space after the last entry in an old buffer, and eliminates buffer content when a last entry from the buffer does not coincide with the beginning of a known word in a dictionary. The device decides the position to place space between words by repeating operation until all content of every buffer is eliminated or until carriage return or a character like a period is stored in each buffer, recomparing a last entry from each buffer with the dictionary, eliminating an optional buffer which has a last entry that does not belong to words in the dictionary or that does not end with space followed by an end character, and executing at least either keeping or output of the remaining words.
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公开(公告)号:JPH06214538A
公开(公告)日:1994-08-05
申请号:JP10691393
申请日:1993-05-07
Applicant: APPLE COMPUTER
Inventor: ROORENSU EI TONPUSON , ERITSUKU EI BAADEN
Abstract: PURPOSE: To provide a computer system for providing an integrated video and graphic display including two individual buffers, i.e., one for video and the other for graphics. CONSTITUTION: Video data stored in the video buffer 40A and graphic data stored in the graphic buffer 40B may be different in the pixel depths. The data are transferred from the video buffer 40A to a video-processing path, and the graphic data are transferred to a graphic-processing path. The data may be transferred from the buffers at different speeds, so that the pixel transfer speeds along the processing paths are equal to each other. Pixels from the respective processing paths may be combined to generate integrated pixels for video and graphic displays.
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公开(公告)号:JPH063913B2
公开(公告)日:1994-01-12
申请号:JP6388286
申请日:1986-03-20
Applicant: APPLE COMPUTER
Inventor: RONARUDO AARU HOTSUHISUPURUNGU , ROORENSU EI KENYON JUNIA , ARAN BII OTSUPENHAIMAA , GAASHARAN ESU SHIDO
IPC: H04L12/413 , H04L12/40
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公开(公告)号:JPH05298454A
公开(公告)日:1993-11-12
申请号:JP35535792
申请日:1992-12-21
Applicant: APPLE COMPUTER
Inventor: ANSONII MASUTAASON
IPC: G09G5/00 , G06T1/00 , G06T1/60 , G06T5/00 , G06T11/00 , G09G5/02 , G09G5/39 , G09G5/393 , G06F15/72 , G06F15/64 , G06F15/66 , G06F15/68
Abstract: PURPOSE: To reduce the size of a display memory required for a computer system capable of making color display. CONSTITUTION: A device 16 which converts the display of color pixels of a 24-bit color format into the display of a 15-bit color format is provided with individual circuits for data indicating each component of colors and each circuit is incorporated with a device which selectively increases the values of the five highest-order bits of a value indicating each component of the colors, a device which makes the device that selectively increases the five highest-order bits generate a signal, and a device which selectively enables a device to respond to the value of the lowest-order bit in accordance with the target pattern of the pixels.
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