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公开(公告)号：US20240164110A1
公开(公告)日：2024-05-16
申请号：US17783627
申请日：2021-12-23
Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY , INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
Inventor： Weixing HUANG , Huilong ZHU
IPC: H10B51/30
CPC classification number: H10B51/30
Abstract: A semiconductor device, including a substrate, a first electrode layer, a functional layer, and a second electrode layer. The functional layer is located between the first electrode layer and the second electrode layer, and includes a first region and a second region having a C-shaped structure surrounding the first region. The C-shape structure opens toward a direction that is parallel with the substrate and away from the first region, that is, the C-shaped structure opens toward a distal side. The first region is made of at least germanium, and the second region includes a C-shaped ferroelectric layer and a C-shaped gate that are sequentially stacked. In embodiments of the present disclosure, the C-shaped ferroelectric layer serves as a memory layer of the memory device. A C-shaped channel is capable to increase an electric field within the ferroelectric layer under a fixed gate voltage, so as to increase a memory window of the semiconductor device. Moreover, the C-shaped channel is capable to reduce a gate voltage decreased under a fixed storage window of the whole semiconductor device, so as to reduce power consumption of the semiconductor device. Hence, a performance of the memory device is improved.
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公开(公告)号：US11985811B2
公开(公告)日：2024-05-14
申请号：US18141107
申请日：2023-04-28
Inventor： Zhengyong Zhu , Bokmoon Kang , Guilei Wang , Chao Zhao
IPC: H10B12/00
Abstract: A semiconductor memory device and a manufacturing method thereof, a reading/writing method, an electronic device and a memory circuit are provided. A transistor is provided in each memory cell in the semiconductor memory device. A gate electrode and an auxiliary electrode are provided in the transistor, and the auxiliary electrode is electrically connected to a drain electrode. During a writing operation, a first voltage is applied to the gate electrode through a word line, and an electrical signal is applied to a source electrode through a bit line according to the external input data. During a reading operation, a second voltage is applied to the auxiliary electrode through the word line by using the influence of the voltage on the auxiliary electrode on the threshold voltage of the transistor (the size of the second voltage is between the threshold voltage of the transistor when storing “1” and the threshold voltage of the transistor when storing “0”), and then the data is read by detecting the size of the output current of the field effect transistor.
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33.发明公开公开(公告)号：US20240120382A1
公开(公告)日：2024-04-11
申请号：US18262193
申请日：2021-11-26
Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY , INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
Inventor： Huilong Zhu , Qi Wang
IPC: H01L29/08 , H01L29/04 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786 , H10B12/00
CPC classification number: H01L29/0847 , H01L29/045 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78642 , H01L29/78696 , H10B12/0335 , H10B12/05 , H10B12/315 , H10B12/482 , H10B12/488
Abstract: A storage device includes a substrate, a storage unit array, and word lines extending in the first direction. The storage unit array includes storage units arranged along a first direction and a second direction. Each storage unit includes: an active region extending in a third direction and including a vertical stack of first source/drain, channel and second source/drain layers, and a gate stack between the first and second source/drain layers in a vertical direction and sandwiching the channel layer from at least two opposite sides. First source/drain layers of each column are continuous to form a bit line extending in the second direction in a zigzag shape. Each word line extends in the first direction to intersect the active regions of a respective row, and is electrically connected to the gate stack of each storage unit on two opposite sides of the channel layer.
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公开(公告)号：US11822797B1
公开(公告)日：2023-11-21
申请号：US18304247
申请日：2023-04-20
Inventor： Jin Dai , Yunsen Zhang
CPC classification number: G06F3/0629 , G06F3/0607 , G06F3/0685
Abstract: An object computational storage system, a data processing method, a client end and a storage medium are disclosed, belonging to the field of electrical digital data processing, including a storage control device and a storage chip or a storage disk connected thereto. The storage control device is a computational storage management system, and performs the following processing: receiving an external data processing request, parsing information of a specified storage object, information of a specified function, and information of input data carried by the data processing request; when it is determined that calling the specified function for the specified storage object is supported, calling the specified function to perform computation on data of the specified storage object according to the input data; and returning a computation result to a sender of the data processing request.
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公开(公告)号：US20230171940A1
公开(公告)日：2023-06-01
申请号：US17817671
申请日：2022-08-05
Inventor： Deyuan XIAO , Yong Yu , Guangsu Shao
IPC: H01L27/108
CPC classification number: H01L27/10873 , H01L27/10814 , H01L27/10885
Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of silicon pillars arranged in an array on the substrate; pre-processing the silicon pillar, to form an active pillar, where along a first direction, the active pillar includes a first segment, a second segment, and a third segment that are connected sequentially; forming a gate oxide layer on sidewalls of each of the second segment and the third segment; and forming a gate dielectric layer on the gate oxide layer, where along the first direction, the gate dielectric layer is shorter than the gate oxide layer, and a top surface of the gate dielectric layer is flush with that of the third segment.
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Patent Agency Ranking
公开(公告)号：US20230171939A1
公开(公告)日：2023-06-01
申请号：US17818537
申请日：2022-08-09
Inventor： Deyuan XIAO , Yong YU , Guangsu SHAO
IPC: H01L27/108
CPC classification number: H01L27/10864 , H01L27/10891 , H01L27/10885
Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of silicon pillars on the substrate, where the silicon pillars are arranged as an array; preprocessing the silicon pillar to form an active pillar, where the active pillar includes a first segment, a second segment, and a third segment; forming a first gate oxide layer on sidewalls of the second segment and the third segment; and forming a second gate oxide layer on the first gate oxide layer, where a length of the second gate oxide layer is less than that of the first gate oxide layer, and a thickness of the second gate oxide layer is greater than that of the first gate oxide layer.
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公开(公告)号：US20230154515A1
公开(公告)日：2023-05-18
申请号：US17808404
申请日：2022-06-23
Inventor： Xiaoguang WANG , DINGGUI ZENG , Huihui LI , Jiefang DENG , Kanyu CAO
CPC classification number: G11C11/161 , G11C11/1655 , H01L43/08 , H01L43/02 , H01L27/228 , H01L43/12
Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a transistor, including a control terminal, a first terminal, and a second terminal; a first magnetic memory structure, a bottom electrode of which is electrically connected to the first terminal of the transistor; a second magnetic memory structure, a top electrode of which is electrically connected to the first terminal of the transistor, the bottom electrode of the first magnetic memory structure is located in a same layer with a bottom electrode of the second magnetic memory structure; a first bit line, electrically connected to a top electrode of the first magnetic memory structure; a second bit line, electrically connected to the bottom electrode of the second magnetic memory structure; and a selection line, electrically connected to a second terminal of the transistor.
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公开(公告)号：US20230116546A1
公开(公告)日：2023-04-13
申请号：US17688606
申请日：2022-03-07
Inventor： Leibo LIU , Baofen YUAN , Shouyi YIN , Shaojun WEI
IPC: G06F8/41
Abstract: A method for a compilation, an electronic device and a readable storage medium are provided. The method for a compilation includes analyzing source program data to determine a target irregular branch, generating an update data flow graph according to the target irregular branch, and mapping the update data flow graph to a target hardware to complete the compilation.
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公开(公告)号：US20230066811A1
公开(公告)日：2023-03-02
申请号：US17664242
申请日：2022-05-20
Inventor： Guangsu SHAO , Pan Yuan , Minmin Wu
IPC: H01L21/762 , H01L21/304
Abstract: The present application provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors. The manufacturing method includes: providing a substrate, the substrate including a first semiconductor material layer, a silicon-germanium compound layer and a second semiconductor material layer that are stacked sequentially; forming, in the substrate, first trenches extending along a first direction and second trenches extending along a second direction, and the first trenches and the second trenches separating the substrate into a plurality of spaced pillar structures; doping the pillar structures, such that the silicon-germanium compound layer forms a channel region; and forming a dielectric layer on an outer peripheral surface of each of the pillar structures, and a gate on an outer peripheral surface of the dielectric layer, the gate being opposite to at least a part of the channel region.
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公开(公告)号：US20230029195A1
公开(公告)日：2023-01-26
申请号：US17832883
申请日：2022-06-06
Inventor： Xiaoguang WANG , Huihui Li , Xianqin Hu
Abstract: A semiconductor structure includes: a Magnetic Random Access Memory (MRAM) cell, including a bottom electrode, a Magnetic Tunnel Junction (MTJ) stack and a top electrode; an insulating layer covering a sidewall partially and a top surface of the MRAM cell; a first dielectric layer, a stop layer and a second dielectric layer sequentially stacked on the insulating layer; and a top electrode contact hole penetrating through the second dielectric layer, the stop layer, the first dielectric layer and the insulating layer, and extending to the top electrode, where the top electrode contact hole includes a first portion and a second portion connected with each other in the stop layer, and a radial width of the second portion in contact with the top electrode is gradually decreased with an increase in a depth of the top electrode contact hole. Method for manufacturing the structure and semiconductor memory are also provided.
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