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Patent Agency Ranking
公开(公告)号：US11985811B2
公开(公告)日：2024-05-14
申请号：US18141107
申请日：2023-04-28
Inventor： Zhengyong Zhu , Bokmoon Kang , Guilei Wang , Chao Zhao
IPC: H10B12/00
Abstract: A semiconductor memory device and a manufacturing method thereof, a reading/writing method, an electronic device and a memory circuit are provided. A transistor is provided in each memory cell in the semiconductor memory device. A gate electrode and an auxiliary electrode are provided in the transistor, and the auxiliary electrode is electrically connected to a drain electrode. During a writing operation, a first voltage is applied to the gate electrode through a word line, and an electrical signal is applied to a source electrode through a bit line according to the external input data. During a reading operation, a second voltage is applied to the auxiliary electrode through the word line by using the influence of the voltage on the auxiliary electrode on the threshold voltage of the transistor (the size of the second voltage is between the threshold voltage of the transistor when storing “1” and the threshold voltage of the transistor when storing “0”), and then the data is read by detecting the size of the output current of the field effect transistor.
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公开(公告)号：US20230320071A1
公开(公告)日：2023-10-05
申请号：US18141107
申请日：2023-04-28
Inventor： Zhengyong Zhu , Bokmoon Kang , Guilei Wang , Chao Zhao
IPC: H10B12/00
Abstract: A semiconductor memory device and a manufacturing method thereof, a reading/writing method, an electronic device and a memory circuit are provided. A transistor is provided in each memory cell in the semiconductor memory device. A gate electrode and an auxiliary electrode are provided in the transistor, and the auxiliary electrode is electrically connected to a drain electrode. During a writing operation, a first voltage is applied to the gate electrode through a word line, and an electrical signal is applied to a source electrode through a bit line according to the external input data. During a reading operation, a second voltage is applied to the auxiliary electrode through the word line by using the influence of the voltage on the auxiliary electrode on the threshold voltage of the transistor (the size of the second voltage is between the threshold voltage of the transistor when storing “1” and the threshold voltage of the transistor when storing “0”), and then the data is read by detecting the size of the output current of the field effect transistor.
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公开(公告)号：US20230320070A1
公开(公告)日：2023-10-05
申请号：US18139766
申请日：2023-04-26
Inventor： Zhengyong Zhu , Bokmoon Kang , Guilei Wang , Chao Zhao
IPC: H10B12/00
Abstract: A memory comprises a substrate, and word lines, bit lines and memory cells located on one side of the substrate. Each of the memory cells comprises a transistor comprising: a semiconductor layer comprising a source contact region, a channel region and a drain contact region connected sequentially; a primary gate electrically connected to one of the word lines; a source electrically connected to one of the bit lines and the source contact region of the semiconductor layer, respectively; a drain electrically connected to the drain contact region of the semiconductor layer; and a secondary gate electrically connected to the drain, wherein an orthographic projection of the primary gate on the substrate and an orthographic projection of the secondary gate on the substrate are at least partially overlapped with an orthographic projection of the channel region of the semiconductor layer on the substrate, respectively.
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公开(公告)号：US20240412778A1
公开(公告)日：2024-12-12
申请号：US18700634
申请日：2022-12-21
Inventor： Zhengyong Zhu , Bokmoon Kang , Chao Zhao
IPC: G11C11/4096 , G11C11/406 , G11C11/408 , G11C11/4094
Abstract: A memory cell, an array read-write method, a control chip, a memory, and an electronic device. The memory cell comprises: a first transistor (TR_R) and a second transistor (TR_W); the first transistor comprises a first electrode, a second electrode, a third electrode, and a fourth electrode; the third electrode is a first gate, and the fourth electrode is a second gate; the second transistor comprises a fifth electrode, a sixth electrode, and a seventh electrode; the seventh electrode is a third gate; the first electrode is connected to a read bit line, the second electrode is connected to a reference signal, the first gate is connected to a read word line, the second gate is connected to the fifth electrode; the sixth electrode is connected to a write bit line, the third gate is connected to a write word line.
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公开(公告)号：US11956943B2
公开(公告)日：2024-04-09
申请号：US18139766
申请日：2023-04-26
Inventor： Zhengyong Zhu , Bokmoon Kang , Guilei Wang , Chao Zhao
IPC: H10B12/00
Abstract: A memory comprises a substrate, and word lines, bit lines and memory cells located on one side of the substrate. Each of the memory cells comprises a transistor comprising: a semiconductor layer comprising a source contact region, a channel region and a drain contact region connected sequentially; a primary gate electrically connected to one of the word lines; a source electrically connected to one of the bit lines and the source contact region of the semiconductor layer, respectively; a drain electrically connected to the drain contact region of the semiconductor layer; and a secondary gate electrically connected to the drain, wherein an orthographic projection of the primary gate on the substrate and an orthographic projection of the secondary gate on the substrate are at least partially overlapped with an orthographic projection of the channel region of the semiconductor layer on the substrate, respectively.
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