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    Power semiconductor device structure with vertical PNP transistor
    35.
    发明公开
    Power semiconductor device structure with vertical PNP transistor 失效
    Leistungshalbleiterbauelementstruktur mit vertikalem PNP晶体管

    公开(公告)号：EP0809294A1

    公开(公告)日：1997-11-26

    申请号：EP96830293.5

    申请日：1996-05-21

    Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

    Inventor： Aiello, Natale ,  Patti, Davide ,  Scaccianoce, Salvatore ,  Leonardi, Salvatore

    IPC: H01L27/00 ,  H01L27/082 ,  H01L21/8224

    CPC classification number: H01L27/0821 ,  H01L21/8224

    Abstract: Power semiconductor device structure formed in a chip (100) of semiconductor material consisting of an N-type substrate (103) and an N-type epitaxial layer (118). The structure comprises a P-type insulation region (106, 121) which forms a pocket (124) in which a control circuitry is formed, and a plurality of fully insulated PNP power transistors. Each PNP power transistor comprises a P-type collector region (109, 127) consisting of an buried region (109) between the substrate (103) and the epitaxial layer (118) and a contact region (127); the P region (109, 127) delimits a base N region (130) within which an emitter P region (148) is formed.

    Abstract translation: 功率半导体器件结构形成在由N型衬底（103）和N型外延层（118）组成的半导体材料的芯片（100）中。 该结构包括形成其中形成控制电路的口袋（124）和多个完全绝缘的PNP功率晶体管的P型绝缘区域（106,121）。 每个PNP功率晶体管包括由衬底（103）和外延层（118）之间的掩埋区（109）和接触区（127）组成的P型集电极区（109,127）。 P区域（109,127）限定形成发射极P区域（148）的基极N区域（130）。

    Method and corresponding circuit for detecting an openload
    38.
    发明公开
    Method and corresponding circuit for detecting an openload 失效
    Verfahren undzugehörigerSchaltkreis zur Feststellung einer Schaltungsunterbrechung

    公开(公告)号：EP0743529A1

    公开(公告)日：1996-11-20

    申请号：EP95830204.4

    申请日：1995-05-16

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l. ,  CO.RI.M.ME.

    Inventor： Pulvirenti, Francesco ,  Gariboldi, Roberto

    IPC: G01R31/02 ,  G05B19/042

    CPC classification number: G01R31/026 ,  G05B19/0423

    Abstract: The invention relates to a method for detecting an open load by means of a driver having at least one main power transistor (M10) connected to the load (L) and one auxiliary transistor (M11) connected in parallel with the main transistor (M10) between a first power supply voltage reference (Vs) and a second voltage reference (GND), the method providing a comparison between a first voltage (V IN1 ) present on a terminal (S10) connected to the load of the main transistor (M10) and a second voltage (V IN2 ) present on a terminal (S11) of the auxiliary transistor (M11).
    The invention also relates to a circuit for detecting an open load (L), in which the said method is implemented.

    Abstract translation: 本发明涉及一种通过驱动器检测开路负载的方法，所述驱动器具有连接到负载（L）的至少一个主功率晶体管（M10）和与主晶体管（M10）并联连接的一个辅助晶体管（M11） 在第一电源电压基准（Vs）和第二电压基准（GND）之间，提供与存在于连接到主晶体管（M10）的负载的端子（S10）上的第一电压（VIN1）和 存在于辅助晶体管（M11）的端子（S11）上的第二电压（VIN2）。 本发明还涉及一种用于检测开启负载（L）的电路，其中实现了所述方法。

    Fuzzy analog processor with temperature compensation
    39.
    发明公开
    Fuzzy analog processor with temperature compensation 失效
    模拟推理师温度补偿

    公开(公告)号：EP0740260A1

    公开(公告)日：1996-10-30

    申请号：EP95830170.7

    申请日：1995-04-28

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

    Inventor： Bruno, Dario ,  Poluzzi, Rinaldo ,  Manaresi, Nicolo ,  Franchi, Eleonora

    IPC: G06G7/60

    CPC classification number: G06N7/043

    Abstract: The analog processor of this invention can carry out processings independently of the operating temperature and process parameters, in a reliable manner and at high performance levels using fairly simple circuitry.
    To achieve this independence, the processor is basically implemented and integrated with MOS transistors, has both voltage inputs (AI) and outputs (OUT), and includes a biasing section (BIAS) which supplies voltage bias signals (VG), of which at least one is substantially the sum of a voltage proportional to the threshold voltage of the MOS transistors and a reference voltage.
    This reference voltage can be extracted from a reference potential which is stable to temperature and process parameters, for example that produced by a bandgap type of generator.
    A major feature of the processor according to the invention is the linearity of its input-output characteristic relative to that reference voltage. It follows that it may be advantageous to extract that reference voltage by division from a signal indicating the width of the input signal variation range, thereby to achieve compensation for or independence of variations of this range.

    Abstract translation: 本发明的模拟处理器可以使用相当简单的电路以可靠的方式和高性能水平独立于工作温度和工艺参数进行处理。 为了实现这种独立性，处理器基本上实现并与MOS晶体管集成，具有电压输入（AI）和输出（OUT）两者，并且包括提供电压偏置信号（VG）的偏置部分（BIAS），其至少 一个基本上是与MOS晶体管的阈值电压成比例的电压和参考电压的总和。 可以从对温度和工艺参数稳定的参考电位提取该参考电压，例如由带隙型发生器产生的参考电压。 根据本发明的处理器的主要特征是其输入 - 输出特性相对于该参考电压的线性。 因此，通过从指示输入信号变化范围的宽度的信号中分离来提取参考电压可能是有利的，从而实现对该范围的变化的补偿或独立性。

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