Abstract:
Herein described is a driving method for LCD modules having a multiplicity of display elements placed in the intersections of a matrix having a plurality of row electrodes and a plurality of column electrodes. The method comprises a first phase for scanning all the row electrodes of said matrix in an interval of scanning time (NT). The first phase comprises a second phase comprising the generation of a first signal suited to energizing at least one row electrode of the matrix for a first preset interval of time (T), the generation of second signals (C3(t), C5(t)) suited to energizing respectively each column electrode of said matrix simultaneously with the energizing of at least one row electrode. The second signals (C3(t), C5(t)) are suited to determining the grey level of each display element of at least one row electrode energized by means of an alternance of corresponding values distinct signal levels (Von, Voff, V1-V3) for intervals of time (T1on, T1off) comprised in the first preset interval of time (T) by means of a first PWM modulation. The first preset interval of time (T) is lower than the interval of scanning time (NT). The first phase comprises a third phase successive to the second phase and comprising the generation of another first signal suited to energizing at least another row electrode of said matrix for a second preset period of time (T) equal and successive to the first preset interval of time, the generation of third signals (C3(t), C5(t)) suited to energizing each column electrode of the matrix simultaneously to said at least another row electrode; the third signals are suited to determining the grey level of each display element of at least another row electrode energized by means of an altemance of values corresponding to said distinct signal levels (Von, Voff, V1-V3) for intervals of time (T2on, T2off) comprised in said second preset interval of time (T) by means of a second PWM modulation. The second PWM modulation is such to ensure the continuity of the signal level of said second signals (C3(t), C5(t)) and third signals (C3(t), C5(t)) in the passage from the first preset period of time (T) to the second preset period of time (T). (Figure 5).
Abstract:
The present invention refers to a supply system of the driving voltage generator of the rows and of the columns of a liquid crystal display. The supply system comprises first and second generator circuits (D3,D4) which output respective prefixed voltages (V3,V4). Each generator circuit receives two supply voltages. The first generator receives, via one voltage supply terminal, a first voltage (VLCD). The second generator receives, via one voltage supply terminal, a second voltage (GND). The other supply terminals of the generators are each connected to a charge storage device (CTNK), e.g. a capacitor, which acts as a charging tank. Charge stored in the capacitor is shared by both generators, and a control circuit (CONT) causes the voltage across the capacitor to lie within a predefined range.
Abstract:
A method of transmitting symbols of a digital transmission constellation from a set thereof, ordered from a smallest to a greatest number of bits per symbol, may include identifying a first constellation from the set that is configured to communicate with a threshold error rate and has a greatest signal-to-noise ratio smaller than a signal-to-noise ratio of a received signal. The method may also include identifying a second constellation from the set that corresponds to a constellation with a number of bits per symbol immediately greater than the first constellation. The method may further include determining first and second probabilities of use of the first and second constellation that would generate an expected number of erroneous bits corresponding to the threshold error rate. The method may further include transmitting a symbol with a constellation selected randomly between the first and second constellation according to the first and second probabilities, respectively.
Abstract:
The recognition of a frame synchronization pattern or unique word of a received signal may be enhanced using a data-aided estimator of the signal-to-noise ratio (SNR) together with a correlation detector of the unique word to be received. Detecting a frame synchronization pattern or a unique word in a received signal, the SNR is estimated on the received signal with a data-aided SNR estimator using the unique word to be received. If the estimated SNR exceeds a certain threshold, an eventual recognition of the unique word established by a correlation correlator of the receiver is considered reliable. Comparing the SNR with the threshold may be carried out either before or after the correlator has processed the unique word.
Abstract:
There is described a method for estimating the signal-to-noise ratio for a packet transmission and reception system of signals with a known sequence, with M-DPSK modulation. The method comprises the division of N known symbols ( a k ) and of N samples of the received signal ( r ( t )) at the output of the channel into B blocks of L length with B and L positive integer numbers and B greater than one and wherein B is expressed by B = N - L L - O + 1 ≥ N L wherein O indicates the overlapping factor of consecutive blocks having length L and the calculation of the estimation of the signal-to-noise ratio by means of the equation: SNR = L - 1 B ⋅ L ∑ b = 0 B - 1 1 L ∑ k = l b l b + L - 1 r k a k * 2 1 B ∑ b = 0 B - 1 1 L ∑ k = l b l b + L - 1 r k 2 - 1 B ∑ b = 0 B - 1 1 L ∑ k = l b l b + L - 1 r k a k * 2 - 1 L wherein l b = b • (L - O) + l where l is the index denoting the position of the first known symbol of the sequence of length N in the packet, r k is the sample of the received signal at the output of the channel correspondent to the known transmitted symbol, a k is the M-DPSK modulated known transmitted symbol, a * k is the complex conjugated of the M-DPSK modulated known transmitted symbol and SNR indicates the estimation of the signal-to-noise ratio.
Abstract translation:描述了一种用于估计信噪比用于信号的分组发送和接收系统具有已知序列,用M-DPSK调制的方法。 该方法包括和输出处的信道的与B和L的正整数和B长度L的B嵌段所接收信号的N个样本(R(T))的N个已知的符号(AK)的分割大于一 和worin B由乙过表达= N - LL - O + 1‰¥NL worin O表示连续块具有长度L,并且由公式的装置信噪比的估计的计算重叠因子: SNR = L - 1乙
Abstract:
The invention relates to an electronic synchronous/ asynchronous transceiver device (100) for power line communication networks of the type integrated into a single chip and operating from a single supply voltage. The transceiver device includes: at least an internal register (40) that is programmable through a synchronous serial interface (41); at least a line driver for a two-way network communication over power lines implemented by a single ended power amplifier (45) with direct accessible input and output lines that is part of a tunable active filter for the transmission path; and at least a couple of linear regulators (30, 35) for powering with different voltage levels different kind of external controllers linked to the transceiver device (100).
Abstract:
The present invention refers to a system for driving columns of a liquid crystal display comprising a logic circuitry (10) operating in a supply path between a first (VDD) and a second (VSS) supply voltage in which the first supply voltage is (VDD) higher than the second supply voltage (VSS). The logic circuitry (10) is capable of generating starting from the first logic signals (LOW_FRAME, WHITE_PIX) in input second logic signals (CP, CN, CP_N, CN_N) in output whose value is equal to the first (VDD) or second (VSS) supply voltage. The device comprises two elevator devices (11, 12) coupled to the logic circuitry (10) and operating in a supply path between a third supply voltage (VLCD) greater than the first supply voltage (VDD) and the second supply voltage (VSS); the elevator devices (11, 12) are capable of raising the value of the second logic signals (CP, CN, CP_N, CN_N). The device also comprises a first (T11-T12) and a second (T13-T14) pair of transistors shaving different supply paths (VLCD-VA, VB-VSS) and having an output terminal (OUT) in common; the first (T11-T12) and the second (T13-T14) pair of transistors are connected to the elevator devices (11, 12) so as to determine the drive signal of a column. The device comprises turnoff circuitry (15) operating in a supply path between the third (VLCD) and the second supply voltage (VSS) and coupled to the two elevator devices (11, 12). The circuitry (15) is capable of keeping one of the two pairs of transistors (T11-T12, T13-T14) in a turnoff state in the period of time of a frame when the other of the two pairs of transistors (T11-T12, T13-T14) is in operative conditions.