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    1.
    发明公开
    "Supply system of the driving voltage generator of the rows and of the columns of a liquid crystal display" 审中-公开
    “用于驱动液晶显示器的行和列电源系统电压发生器”

    公开(公告)号：EP1324304A1

    公开(公告)日：2003-07-02

    申请号：EP01830810.6

    申请日：2001-12-27

    Applicant: STMicroelectronics S.r.l. ,  Dora S.p.A.

    Inventor： Sala, Leonardo ,  Pulvirenti, Francesco ,  Gariboldi, Roberto

    IPC: G09G3/36

    CPC classification number: G09G3/3696 ,  G09G3/3622 ,  G09G2330/023

    Abstract: The present invention refers to a supply system of the driving voltage generator of the rows and of the columns of a liquid crystal display. The supply system comprises first and second generator circuits (D3,D4) which output respective prefixed voltages (V3,V4). Each generator circuit receives two supply voltages. The first generator receives, via one voltage supply terminal, a first voltage (VLCD). The second generator receives, via one voltage supply terminal, a second voltage (GND). The other supply terminals of the generators are each connected to a charge storage device (CTNK), e.g. a capacitor, which acts as a charging tank. Charge stored in the capacitor is shared by both generators, and a control circuit (CONT) causes the voltage across the capacitor to lie within a predefined range.

    Abstract translation: 本发明涉及到行的驱动电压产生器的供给系统和液晶显示器的列的。 所述供应系统包括第一和第二发生器电路（D3，D4）哪个输出respectivement前缀电压（V3，V4）。 每个发生器电路接收两个电源电压。 第一发生器接收，经由一个电压提供端，第一电压（VLCD）。 第二生成器接收，经由一个电压源端，第二电压（GND）。 发电机的另一电源端子分别连接到电荷存储装置（CTNK），例如 电容器，其用作一个充电罐。 存储在电容器的电荷被两个发生器共享;以及控制电路（CONT）使电容器两端的电压，使之处于预定范围内。

    Voltage multiplier and related operation method
    2.
    发明公开
    Voltage multiplier and related operation method 有权
    Spannungsvervielfacher unddiesbezüglichesBetriebsverfahren

    公开(公告)号：EP1696542A1

    公开(公告)日：2006-08-30

    申请号：EP05425108.7

    申请日：2005-02-28

    Applicant: STMicroelectronics S.r.l. ,  Dora S.p.A.

    Inventor： Pannizzo, Ivo ,  Pulvirenti, Francesco

    IPC: H02M3/07

    CPC classification number: H02M3/073

    Abstract: The present invention describes a voltage multiplier receiving a constant voltage (Vs). The multiplier comprises means (1) suitable for generating at least one first (CK) and one second (XCK) signal in phase opposition between each other and at least one charging section (100, Ai). The latter comprises a first capacitor (C1) of charge transfer having a first terminal coupled to the first signal (CK) and a second capacitor (C2) of charge transfer having a first terminal coupled with the second signal (XCK). The two capacitors (C1, C2) of charge transfer comprise respective parasitic capacitances (Cp1, Cp2) placed between their first terminal and a reference voltage (GND) and the at least one charging section (100, Ai) is coupled with said constant voltage (Vs) and is suitable for producing in output a multiple voltage of the constant voltage. The multiplier comprises output means (OUT, Cs) receiving said multiple voltage of the input voltage and being suitable for supplying a substantially constant output voltage (Vout) which is multiple of the constant voltage (Vs). The multiplier comprises means (10) suitable for connecting the parasitic capacitances (Cp1, Cp2) to carry out the charge transfer from one parasitic capacitance to the other.

    Abstract translation: 本发明描述了接收恒定电压（Vs）的电压倍增器。 乘法器包括适于产生彼此相对的至少一个第一（CK）和一个第二（XCK）信号的装置（1）和至少一个充电部分（100A）。 后者包括电荷转移的第一电容器（C1），其具有耦合到第一信号（CK）的第一端子和具有与第二信号（XCK）耦合的第一端子的电荷转移的第二电容器（C2）。 电荷转移的两个电容器（C1，C2）包括放置在它们的第一端子和参考电压（GND）之间的相应的寄生电容（Cp1，Cp2），并且至少一个充电部分（100，Ai）与所述恒定电压 （Vs），并且适用于在输出中产生恒定电压的多个电压。 乘法器包括接收输入电压的多个电压的输出装置（OUT，Cs），并且适于提供恒定电压（Vs）的倍数的基本恒定的输出电压（Vout）。 乘法器包括适于连接寄生电容（Cp1，Cp2）的装置（10），以执行从一个寄生电容到另一个寄生电容的电荷转移。

    Method and circuit to perform a trimming phase on electronic circuits
    6.
    发明公开
    Method and circuit to perform a trimming phase on electronic circuits 有权
    Verfahren und Vorrichtung zur Trimmung von elektronischen Schaltungen

    公开(公告)号：EP1120828A1

    公开(公告)日：2001-08-01

    申请号：EP00830059.2

    申请日：2000-01-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pulvirenti, Francesco

    IPC: H01L21/66 ,  H03K17/693

    CPC classification number: G11C17/18 ,  G01R31/31701

    Abstract: The invention relates to a method and a circuit for carrying out a trimming operation on integrated circuits (2) having a trimming circuit portion (1) which includes memory elements (10) and a means (8) of modifying the state of said memory elements (10), at least a first input or supply pin (IN), an output pin (OUT), and a second supply pin (GND). The method comprises the following steps:

    enabling a single pin (OUT) to receive trimming data by biasing the pin to outside its operating range;
    to acquire such data, obtaining a clock signal from a division of the bias potential of the trimming pin (OUT);
    obtaining the logic value of the trimming data from a different division of the bias potential of said pin (OUT);
    enabling serial acquisition of the data according to the clock signal; and
    transferring the data to the means (8) of modifying the state of the memory elements (10).

    Advantageously, the data are also transferred into a selection logic (11), by-passing the means (8) for modifying the state of the memory elements (10), on the occurrence of a simulated trimming operation.

    Abstract translation: 本发明涉及一种用于对具有修整电路部分（1）的集成电路（2）进行修整操作的方法和电路，该修整电路部分（1）包括存储元件（10）和修改所述存储元件的状态的装置（8） （10），至少第一输入或电源引脚（IN），输出引脚（OUT）和第二电源引脚（GND）。 该方法包括以下步骤：通过将引脚偏置在其工作范围之外，使单个引脚（OUT）能够接收修剪数据; 获取这样的数据，从修整引脚（OUT）的偏置电位的除法获得时钟信号; 从所述引脚（OUT）的偏置电位的不同分割获得修整数据的逻辑值; 使得能够根据时钟信号串行获取数据; 以及将数据传送到修改存储元件（10）的状态的装置（8）。 有利地，在模拟修整操作的发生时，数据也被转移到选择逻辑（11）中，绕过用于修改存储元件（10）的状态的装置（8）。

    DC-DC converter usable as a battery charger, and method for charging a battery
    7.
    发明公开
    DC-DC converter usable as a battery charger, and method for charging a battery 有权
    ALS BATTERIELADER BENUTZBARER GLEICHSTROMWANDLER，UND VERFAHREN ZUM AUFLADEN EINER BATTERIE

    公开(公告)号：EP1049230A1

    公开(公告)日：2000-11-02

    申请号：EP99830258.2

    申请日：1999-04-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pappalardo, Salvatore ,  Pulvirenti, Francesco

    IPC: H02J7/00

    CPC classification number: H02J7/0052

    Abstract: The DC-DC converter (1') comprises a current error amplifier (34') and a voltage error amplifier (30) connected in parallel to control the charging phase of the battery (18), during which a charging current (IBAT) is supplied to the battery (18) to bring the voltage (VBAT) of the battery (18) gradually up to a full charge voltage (VFIN); a charging interruption stage (QA, QB, MS5) for interrupting the charging phase before the voltage (VBAT) of the battery has reached the full charge voltage (VFIN); and an activation stage (104, 106) for activating the charging interruption stage (QA, QB, MS5) when the full charge voltage (VFIN) is close to the supply potential (VCC) at which the supply line (6) of the current error amplifier (34') is set.

    Abstract translation: DC-DC转换器（1'）包括并联连接的电流误差放大器（34'）和电压误差放大器（30），以控制电池（18）的充电阶段，在此期间充电电流（IBAT）为 提供给电池（18）以使电池（18）的电压（VBAT）逐渐升至满充电电压（VFIN）; 用于在电池电压（VBAT）达到完全充电电压（VFIN）之前中断充电阶段的充电中断阶段（QA，QB，MS5）; 以及当所述满充电电压（VFIN）接近所述电源（6）的所述电源电位（VCC）时，用于激活所述充电中断级（QA，QB，MS5）的激活级（104,106） 设置误差放大器（34'）。

    Method and circuit to perform a trimming phase on electronic circuits
    10.
    发明授权
    Method and circuit to perform a trimming phase on electronic circuits 有权
    用于电子电路的修整的方法和设备

    公开(公告)号：EP1120828B1

    公开(公告)日：2005-04-06

    申请号：EP00830059.2

    申请日：2000-01-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pulvirenti, Francesco

    IPC: H01L21/66 ,  H03K17/693

    CPC classification number: G11C17/18 ,  G01R31/31701

    Abstract: The invention relates to a method and a circuit for carrying out a trimming operation on integrated circuits (2) having a trimming circuit portion (1) which includes memory elements (10) and a means (8) of modifying the state of said memory elements (10), at least a first input or supply pin (IN), an output pin (OUT), and a second supply pin (GND). The method comprises the following steps: enabling a single pin (OUT) to receive trimming data by biasing the pin to outside its operating range; to acquire such data, obtaining a clock signal from a division of the bias potential of the trimming pin (OUT); obtaining the logic value of the trimming data from a different division of the bias potential of said pin (OUT); enabling serial acquisition of the data according to the clock signal; and transferring the data to the means (8) of modifying the state of the memory elements (10). Advantageously, the data are also transferred into a selection logic (11), by-passing the means (8) for modifying the state of the memory elements (10), on the occurrence of a simulated trimming operation.

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