公开(公告)号：WO2004003883A1

公开(公告)日：2004-01-08

申请号：PCT/EP2003/006639

申请日：2003-06-23

Applicant: STMICROELECTRONICS S.R.L. ,  DORA S.P.A. ,  PAPPALARDO, Salvatore ,  PULVIRENTI, Francesco ,  PRIVITERA, Salvatore ,  SALA, Leonardo

Inventor： PAPPALARDO, Salvatore ,  PULVIRENTI, Francesco ,  PRIVITERA, Salvatore ,  SALA, Leonardo

IPC: G09G3/36

CPC classification number: G09G3/3681 ,  G09G3/3674

Abstract: The present invention describes a system for driving rows of a liquid crystal display comprising at least one module (10) for driving one single row of the liquid crystal display. The module comprises an inverter (T11-T12) operating in a supply path between a first (21) and a second (22) supply line of the system, where the first supply line (21) comprises first means (S1) capable of connecting it to a first (VLCD) or to a second (VA) supply voltage and the second supply line (22) comprises second means (S2) capable of connecting it to a third (VB) or to a fourth (VSS) supply voltage. The inverter (T11-T12) is driven by a logic circuitry (11-12) and sends in output (OUT) a drive signal for one single row of the liquid crystal display.

Abstract translation: 本发明描述了一种用于驱动液晶显示器行的系统，包括用于驱动液晶显示器的一行的至少一个模块（10）。 该模块包括在系统的第一（21）和第二（22）电源线之间的供应路径中工作的逆变器（T11-T12），其中第一供电线（21）包括能够连接的第一装置（S1） 第二电源线（22）包括能够将其连接到第三（VB）或第四（VSS）电源电压的第二装置（S2）。 逆变器（T11-T12）由逻辑电路（11-12）驱动，并向输出（OUT）发送一行液晶显示器的驱动信号。

公开(公告)号：WO2004003882A1

公开(公告)日：2004-01-08

申请号：PCT/EP2003/006638

申请日：2003-06-23

Applicant: STMICROELECTRONICS S.R.L. ,  DORA S.P.A. ,  PAPPALARDO, Salvatore ,  PULVIRENTI, Francesco ,  PRIVITERA, Salvatore ,  SALA, Leonardo

Inventor： PAPPALARDO, Salvatore ,  PULVIRENTI, Francesco ,  PRIVITERA, Salvatore ,  SALA, Leonardo

IPC: G09G3/36

CPC classification number: G09G3/3685 ,  G09G2330/021

Abstract: The present invention refers to a system for driving columns of a liquid crystal display comprising a logic circuitry (10) operating in a supply path between a first (VDD) and a second (VSS) supply voltage in which the first supply voltage is (VDD) higher than the second supply voltage (VSS). The logic circuitry (10) is capable of generating starting from the first logic signals (LOW_FRAME, WHITE_PIX) in input second logic signals (CP, CN, CP_N, CN_N) in output whose value is equal to the first (VDD) or second (VSS) supply voltage. The device comprises two elevator devices (11, 12) coupled to the logic circuitry (10) and operating in a supply path between a third supply voltage (VLCD) greater than the first supply voltage (VDD) and the second supply voltage (VSS); the elevator devices (11, 12) are capable of raising the value of the second logic signals (CP, CN, CP_N, CN_N). The device also comprises a first (T11-T12) and a second (T13-T14) pair of transistors shaving different supply paths (VLCD-VA, VB-VSS) and having an output terminal (OUT) in common; the first (T11-T12) and the second (T13-T14) pair of transistors are connected to the elevator devices (11, 12) so as to determine the drive signal of a column. The device comprises turnoff circuitry (15) operating in a supply path between the third (VLCD) and the second supply voltage (VSS) and coupled to the two elevator devices (11, 12). The circuitry (15) is capable of keeping one of the two pairs of transistors (T11-T12, T13-T14) in a turnoff state in the period of time of a frame when the other of the two pairs of transistors (T11-T12, T13-T14) is in operative conditions.

Abstract translation: 本发明涉及一种用于驱动液晶显示器列的系统，其包括在第一电源电压（VDD）和第二（VSS）电源电压之间的供电路径中工作的逻辑电路（10），其中第一电源电压为（VDD ）高于第二电源电压（VSS）。 逻辑电路（10）能够从其值等于第一（VDD）或第二（VDD）的输出中的输入第二逻辑信号（CP，CN，CP_N，CN_N）中的第一逻辑信号（LOW_FRAME，WHITE_PIX） VSS）电源电压。 该装置包括耦合到逻辑电路（10）并且在大于第一电源电压（VDD）和第二电源电压（VSS））的第三电源电压（VLCD）之间的供电路径中操作的两个电梯装置（11,12） ; 电梯装置（11,12）能够提高第二逻辑信号（CP，CN，CP_N，CN_N）的值。 该器件还包括共用剃须不同电源路径（VLCD-VA，VB-VSS）并具有输出端（OUT）的第一（T11-T12）和第二（T13-T14）对晶体管; 第一（T11-T12）和第二（T13-T14）晶体管对连接到电梯装置（11,12），以便确定列的驱动信号。 该装置包括在第三（VLCD）和第二电源电压（VSS）之间的供应路径中工作并耦合到两个电梯装置（11,12）的关闭电路（15）。 当两对晶体管（T11-T12）中的另一对晶体管（T11-T12）的一对晶体管（T11-T12-T12）中的另一个晶体管 ，T13-T14）处于工作状态。

公开(公告)号：EP1532614A1

公开(公告)日：2005-05-25

申请号：EP03761493.0

申请日：2003-06-23

Applicant: STMicroelectronics S.r.l. ,  Dora S.p.A.

Inventor： PAPPALARDO, Salvatore ,  PULVIRENTI, Francesco ,  PRIVITERA, Salvatore ,  SALA, Leonardo

IPC: G09G3/36

CPC classification number: G09G3/3685 ,  G09G2330/021

Abstract: The present invention refers to a system for driving columns of a liquid crystal display comprising a logic circuitry (10) operating in a supply path between a first (VDD) and a second (VSS) supply voltage in which the first supply voltage is (VDD) higher than the second supply voltage (VSS). The logic circuitry (10) is capable of generating starting from the first logic signals (LOW_FRAME, WHITE_PIX) in input second logic signals (CP, CN, CP_N, CN_N) in output whose value is equal to the first (VDD) or second (VSS) supply voltage. The device comprises two elevator devices (11, 12) coupled to the logic circuitry (10) and operating in a supply path between a third supply voltage (VLCD) greater than the first supply voltage (VDD) and the second supply voltage (VSS); the elevator devices (11, 12) are capable of raising the value of the second logic signals (CP, CN, CP_N, CN_N). The device also comprises a first (T11-T12) and a second (T13-T14) pair of transistors shaving different supply paths (VLCD-VA, VB-VSS) and having an output terminal (OUT) in common; the first (T11-T12) and the second (T13-T14) pair of transistors are connected to the elevator devices (11, 12) so as to determine the drive signal of a column. The device comprises turnoff circuitry (15) operating in a supply path between the third (VLCD) and the second supply voltage (VSS) and coupled to the two elevator devices (11, 12). The circuitry (15) is capable of keeping one of the two pairs of transistors (T11-T12, T13-T14) in a turnoff state in the period of time of a frame when the other of the two pairs of transistors (T11-T12, T13-T14) is in operative conditions.

公开(公告)号：EP1518219A1

公开(公告)日：2005-03-30

申请号：EP03740320.1

申请日：2003-06-23

Applicant: STMicroelectronics S.r.l. ,  Dora S.p.A.

Inventor： PAPPALARDO, Salvatore ,  PULVIRENTI, Francesco ,  PRIVITERA, Salvatore ,  SALA, Leonardo

IPC: G09G3/36

CPC classification number: G09G3/3681 ,  G09G3/3674

Abstract: The present invention describes a system for driving rows of a liquid crystal display comprising at least one module (10) for driving one single row of the liquid crystal display. The module comprises an inverter (T11-T12) operating in a supply path between a first (21) and a second (22) supply line of the system, where the first supply line (21) comprises first means (S1) capable of connecting it to a first (VLCD) or to a second (VA) supply voltage and the second supply line (22) comprises second means (S2) capable of connecting it to a third (VB) or to a fourth (VSS) supply voltage. The inverter (T11-T12) is driven by a logic circuitry (11-12) and sends in output (OUT) a drive signal for one single row of the liquid crystal display.

公开(公告)号：WO2005098806A1

公开(公告)日：2005-10-20

申请号：PCT/IT2004/000191

申请日：2004-04-08

Applicant: STMICROELECTRONICS S.R.L. ,  TOHOKU PIONEER CORPORATION ,  PULVIRENTI, Francesco ,  BONTEMPO, Gregorio ,  MASAKI, Murakata ,  AKINORI, Hayafuji

Inventor： PULVIRENTI, Francesco ,  BONTEMPO, Gregorio ,  MASAKI, Murakata ,  AKINORI, Hayafuji

IPC: G09G3/22

CPC classification number: G09G3/3216 ,  G09G3/22 ,  G09G3/3283 ,  G09G2320/029 ,  G09G2320/041 ,  G09G2320/043 ,  G09G2330/021 ,  G09G2330/028

Abstract: An OLED (organic light-emitting diode) passive-matrix display (26) includes a display portion (10) and a driver portion (28). The display portion (10) includes a matrix of OLEDs (13) for displaying information. The driver portion (28) includes a monitor circuit (32) and a voltage adjusting circuit (34). The voltage adjusting circuit (34) has a power-up portion (36) that generates a supply voltage (VH) based on a reference voltage (VREF). In response to an indication to switch modes, the voltage adjusting circuit (34) switches to an operational mode wherein the supply voltage (VH) is generated based on the maximum voltage drop read across the OLEDs (13).

Abstract translation: OLED（有机发光二极管）无源矩阵显示器（26）包括显示部分（10）和驱动器部分（28）。 显示部分（10）包括用于显示信息的OLED（13）矩阵。 驱动器部分（28）包括监控电路（32）和电压调节电路（34）。 电压调节电路（34）具有基于参考电压（VREF）产生电源电压（VH）的上电部分（36）。 响应于切换模式的指示，电压调节电路（34）切换到操作模式，其中基于跨越OLED（13）读取的最大电压降产生电源电压（VH）。

公开(公告)号：EP4443265A1

公开(公告)日：2024-10-09

申请号：EP24164192.7

申请日：2024-03-18

Applicant: STMicroelectronics S.r.l.

Inventor： BIMBI, Cesare ,  PRIVITERA, Salvatore Giuseppe ,  PULVIRENTI, Francesco

IPC: G05F3/24 ,  G05F1/575

CPC classification number: G05F3/24 ,  G05F1/575

Abstract: A voltage regulation circuit (20;20';60) receiving as input an input voltage (VCC), in particular a DC voltage supply, and outputting a regulated voltage (VREG),
comprising a voltage reference circuit (50;90) configured to supply a reference voltage (VREF) which is independent, in particular with respect to temperature variations
said voltage regulation circuit (20;20';60) comprising a first circuit branch (B1) and a second circuit branch (B2) in parallel coupled between said input voltage (VCC) and ground (GND),
said first branch (B1) comprising
a current generator (31; 71) comprising a first depletion MOSFET transistor (QD2), which gate source voltage is a PTAT (Proportional To Absolute Temperature) voltage, coupled between said input voltage (VCC) and the voltage reference circuit (50;90),
said voltage reference circuit (50;90) comprising a first enhancement MOSFET transistor (QE2), which gate source voltage is a CTAT (Complementary To Absolute Temperature) voltage, coupled to the ground (GND) by its source through a source resistor (R5), on which a reference voltage (VREF), sum of the PTAT voltage drop (VP) on the source resistor (R5) and of the gate source voltage (VGS(QE2)) of the enhancement MOSFET transistor (QE2) being formed, said first enhancement MOSFET transistor (QE2) being arranged on said first branch (B1) and coupled by the drain to said first depletion MOSFET transistor (QD2) in a control node (C), said control node (C) being coupled to the gate of said first enhancement MOSFET transistor (QE2),
said first depletion MOSFET transistor (QD2) injecting a PTAT current (ID2) in said first branch (B1) determining a PTAT voltage drop (VP) on said source resistor (R5),
said second branch (B2) comprising an output stage (33; 73) coupled between said voltage to regulate (VCC) and an output node (REG) on which said regulated voltage (VREG) is taken, said output stage (33) comprising a second depletion MOSFET transistor (QD4) on which output is taken said output node (REG), a resistive voltage divider (40; 80) being coupled to said output node (REG), outputting on a respective divider output node (A) a divided output regulated voltage (VREG) which is inputted as the process variable of a negative feedback loop (QE2; 75) which is also coupled to said reference voltage (VREF), the output of said negative feedback loop (QE2; 75) controlling the gate of said second MOSFET transistor (QD4).

公开(公告)号：EP3934097A1

公开(公告)日：2022-01-05

申请号：EP21179806.1

申请日：2021-06-16

Applicant: STMicroelectronics S.r.l.

Inventor： FONTANA, Marco Giovanni ,  RIVA, Marco ,  PULVIRENTI, Francesco ,  CANTONE, Giuseppe

IPC: H03K17/082 ,  H03K17/0812 ,  H03K17/06 ,  H02M1/00 ,  H02M1/08

Abstract: A circuit (HBD) comprises a first (100a) and a second (100b) input supply nodes configured to receive a supply voltage ( V CC ) therebetween. The circuit comprises a high-side driver circuit (12a) configured to be coupled to a high-side switch (HS) of a half-bridge circuit, the high-side driver circuit (12a) configured to produce a first output control signal between a first high-side output node (120a) and a second high-side output node (102a). The circuit comprises a low-side driver circuit (12b) configured to be coupled to a low-side switch (LS) of the half-bridge circuit, the low-side driver circuit (12b) configured to produce a second output control signal between a first low-side output node (120b) and a second low-side output node (102b). The circuit comprises a floating supply node (104) configured to receive a floating supply voltage ( V CB ) applied between the floating supply node (104) and the second high-side output node (102a) to power the high-side driver circuit (12a). The circuit comprises a bootstrap diode (D3) between the first input supply node (100a) and an intermediate supply node (106), and a current limiter circuit (Q1', Dl', 62) between the intermediate supply node (106) and the floating supply node (104). The current limiter circuit (Q1', Dl', 62) is configured to sense the floating supply voltage ( V CB ) and to counter a current flow from the intermediate supply node (106) to the floating supply node (104) as a result of the floating supply voltage ( V CB ) reaching a threshold value.

公开(公告)号：EP3907888A1

公开(公告)日：2021-11-10

申请号：EP21169736.2

申请日：2021-04-21

Applicant: STMicroelectronics S.r.l.

Inventor： BOGNANNI, Fabrizio ,  CAGGEGI, Giovanni ,  CANTONE, Giuseppe ,  MARANO, Vincenzo ,  PULVIRENTI, Francesco

IPC: H03K19/0185 ,  H03K17/06 ,  H02M7/5387

Abstract: A circuit (21, 22) to transfer a command signal (CS) in a circuit (20) comprising circuit stages which are voltage supplied by different voltage domains (VCC, GND; FS, FG) including
a first voltage domain (VCC, GND) comprising first voltage levels represented by a first voltage supply (VCC) and a first voltage reference (GND), in particular a DC voltage supply and a DC ground, and
a second voltage domain (FS, FG) comprising second voltage levels represented by a second voltage supply (VFS) and a second voltage reference (V FG ), in particular a floating supply and a floating ground, and
said circuit (21, 22) to transfer a signal (CS) operating according to the first voltage domain (VCC, GND) to a stage (HS_DRV, PW1) operating according to the second voltage domain (FS, FG),
said circuit (21, 22) to transfer a command signal (CS) including a logic component (224) operating according to the second voltage domain (FS, FG) logically driving said stage (HS_DRV, PW1), and a level shifting circuit (22; 32; 42) coupled to the second voltage supply (FS) and to the first ground reference (GND),
said level shifting circuit (22; 32; 42) including two paths coupled between said second voltage supply (FS) and to the first ground reference (GND), each including a high voltage transistor (221a, 221b) coupled through a respective resistor (223a, 223b) to the second voltage supply (FS) and through a respective commanded current generator (222a; 222b) to the first ground reference (GND), each path being coupled to a respective input (S,R) of the logic component (224), said commanded current generator (222a; 222b) being commanded by pulse signals (Tp1, Tp2) generated by a pulse generator (225) on the basis of said command signal (CS),
characterized in that
said level shifting circuit (32; 42) includes a negative bootstrap circuit (C1, INV1, INV2, C2, INV3, INV4; Cpump, SINV, FINV, 228, 229) including at least a pump capacitor (C1, C2; Cpump) arranged between the current generators (222a; 222b) and the first ground reference (GND) and configured to shift at a negative voltage said first ground reference (GND) synchronically with the activation of the respective commanded current generator (222a; 222b).