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    Method and circuit for controlling the charge of a bootstrap capacitor in a switching step-down regulator
    33.
    发明公开
    Method and circuit for controlling the charge of a bootstrap capacitor in a switching step-down regulator 失效
    方法和电路，用于控制在一个开关电压调节器减少的电荷的自举电容的

    公开(公告)号：EP0822475A1

    公开(公告)日：1998-02-04

    申请号：EP96830431.1

    申请日：1996-07-31

    Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

    Inventor： Borghi, Maria Rosa ,  Magazzu', Antonio

    IPC: G05F1/00 ,  H02M3/155

    CPC classification number: G05F1/465

    Abstract: The invention concerns a method of controlling the charging of a bootstrap capacitance (C BOOT ) incorporated into a switching regulator (2) of a power transistor (M1). The method consists of carrying out, at each switching cycle, a comparison between the voltage value (V CBOOT ) at the bootstrap capacitance (C BOOT ) and a predetermined threshold voltage (Vs), to change the mode of operation of the regulator following said comparison.
    More particularly, the control on the transistor (M1) is taken off the regulator (2) when the voltage (V CBOOT ) at the bootstrap capacitance (C BOOT ) is lower than the threshold voltage (Vs), while the transistor (M1) is forced into the "on" state through a full cycle. In this way, the minimum current (I MIN ) to operate the regulator (2) can be minimised.

    Abstract translation: 本发明涉及控制掺入到功率晶体管（M1）的开关调节器（2）的自举电容（C BOOT）的充电的方法。 进行，在每个开关周期的方法besteht，在自举电容（C BOOT）的电压值（VCBOOT）和预定的阈值电压（Vs）之间的比较，改变调节器按照所述比较的操作模式。 更具体地，在晶体管（M1）的控制被取出的调节器（2）当在自举电容（C BOOT）上的电压（VCBOOT）大于阈值电压（Vs）降低，而晶体管（M1）被强制 通过将一个完整周期的“开”状​​态。 以这种方式，最小电流（I MIN）来操作调节器（2）可被最小化。

    Semiconductor integrated capacitive acceleration sensor and relative fabrication method
    34.
    发明公开
    Semiconductor integrated capacitive acceleration sensor and relative fabrication method 失效
    集成电容半导体加速度传感器，以及其制备方法

    公开(公告)号：EP0822415A1

    公开(公告)日：1998-02-04

    申请号：EP96830438.6

    申请日：1996-07-31

    Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

    Inventor： Ferrari, Paolo ,  Foroni, Mario ,  Vigna, Benedetto ,  Villa, Flavio

    IPC: G01P15/00 ,  G01P15/08 ,  G01P15/125

    CPC classification number: G01P15/0802 ,  G01P15/125 ,  G01P2015/0814

    Abstract: The acceleration sensor is formed in a monocrystalline silicon wafer (4) forming part of a dedicated SOI substrate (50) presenting a first (1) and second (4) monocrystalline silicon wafer separated by an insulating layer (2) having an air gap (3). A well (15) is formed in the second wafer (4), over the air gap (3), and is subsequently trenched up to the air gap to release the monocrystalline silicon mass (23) forming the movable mass (24) of the sensor; the movable mass (24) has two numbers of movable electrodes (28a, 28b) facing respective pluralities of fixed electrodes (29a, 29b). In the idle condition, each movable electrode (28) is separated by different distances from the two fixed electrodes (29) facing the movable electrode.

    Abstract translation: 加速度传感器在单晶硅晶片上形成（4）形成（50）呈现一个专用的SOI衬底的一部分的第一（1），并通过在在空气隙绝缘（2），其具有层分离的第二（4）单晶硅晶片（ 3）。 良好（15）形成在所述第二晶片（4），在所述空气间隙（3），并随后被开槽到空气间隙，以释放成形的可动质量块（24）的单晶硅的质量（23） 传感器; 运动质量块（24）具有可动电极的两个数（28A，28B）的面向固定电极的多个respectivement（29A，29B）。 在空闲状态下，每个可移动电极（28）由从面向可动电极的两个固定电极（29）不同的距离分离。

    Circuit for ratiometric processing and driving
    35.
    发明公开
    Circuit for ratiometric processing and driving 失效
    Schaltung zurverhältniskonstantenSignalverarbeitung

    公开(公告)号：EP0822392A1

    公开(公告)日：1998-02-04

    申请号：EP96830421.2

    申请日：1996-07-30

    Applicant: SGS-THOMSON MICROELECTRONICS s.r.l. ,  MAGNETI MARELLI S.p.A.

    Inventor： Poletto, Vanni ,  Poma, Alberto ,  Morelli, Marco

    IPC: G01F23/00 ,  G01F23/30

    CPC classification number: G01F23/0061 ,  G01F23/30

    Abstract: The electronic interface circuit can perform ratiometric processing and driving of a signal (Rj) generated by a fuel-level detector (GAL) of a vehicle. The circuit uses a current mirror (S) configured so as to send one half (Ij) of the output current (IL) to the input resistance (Rj) and one half of the output current (IL) to earth. The current mirror (S) is controlled by a voltage (Vj) taken from the input resistance (Rj) and by a voltage taken from a resistive divider (Ra1, Ra2), the latter voltage having been filtered by a low-pass filter (FIL), so as to achieve ratiometric processing of the input signal (Rj).

    Abstract translation: 电子接口电路可以执行比例计算处理和驱动由车辆的燃料液位检测器（GAL）产生的信号（Rj）。 电路使用电流镜（S），其配置为将输出电流（IL）的一半（Ij）发送到输入电阻（Rj），并将一半输出电流（IL）发送到地。 电流镜（S）由从输入电阻（Rj）取得的电压（Vj）和取自电阻分压器（Ra1，Ra2）的电压控制，后一电压由低通滤波器 FIL），以便实现输入信号（Rj）的比例处理。

    Output stage for a memory device and for low voltage applications
    36.
    发明公开
    Output stage for a memory device and for low voltage applications 失效
    AusgabestufefürSpeicheranlage undfürNiederspannungsanwendungen

    公开(公告)号：EP0821362A1

    公开(公告)日：1998-01-28

    申请号：EP96830411.3

    申请日：1996-07-24

    Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

    Inventor： Campardo, Giovanni ,  Zanardi, Stefano ,  Ghilardelli, Andrea

    IPC: G11C7/00

    CPC classification number: G11C7/1057 ,  G11C7/1051 ,  G11C7/1069

    Abstract: The present invention relates to an output stage for an electronic memory device and for low supply-voltage applications and is the type comprising a final stage (10) of the pull-up/pull-down type made up of a complementary pair of transistors (Mu,Md) inserted between a primary reference supply voltage (Vcc) and a secondary reference voltage (GND) and a voltage regulator (11) for the control terminals (O1,O2) of said transistors. The regulator (11) is a voltage booster using at least one bootstrap capacitor to increase the current flowing in the final stage (10) by boosting the voltage applied to said control terminals (O1,O2).

    Abstract translation: 本发明涉及电子存储器件的输出级和低电源电压应用，并且是包括由互补晶体管构成的上拉/下拉型的最后级（10） Mu，Md）插入在所述晶体管的控制端子（O1，O2）的初级参考电源电压（Vcc）和次级参考电压（GND）和电压调节器（11）之间。 调节器（11）是使用至少一个自举电容器的升压器，其通过升高施加到所述控制端子（O1，O2）的电压来增加在最后级（10）中流动的电流。

    MPEG-2 decoding with a reduced RAM requisite by ADPCM recompression before storing MPEG-2 decompressed data optionally after a subsampling algorithm
    39.
    发明公开
    MPEG-2 decoding with a reduced RAM requisite by ADPCM recompression before storing MPEG-2 decompressed data optionally after a subsampling algorithm 失效
    MPEG-2通过ADPCM再压缩解压缩的MPEG-2数据的存储之前减少RAM需要解码，任选的后Unterablastungsalgorithm

    公开(公告)号：EP0817498A1

    公开(公告)日：1998-01-07

    申请号：EP96830367.7

    申请日：1996-06-28

    Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

    Inventor： Pau, Danilo

    IPC: H04N7/50

    CPC classification number: H04N19/428 ,  H04N19/423 ,  H04N19/61

    Abstract: The video memory requisite of an MPEG decoder effecting a decompression of the I, P and optionally also of the B picture according to the MPEG compression algorithm and requiring the storing in respective buffers organized in said video memory of the respective MPEG- decompressed data, may be dynamically reduced by subsampling and recompressing according to a ADPCM algorithm at least the data pertaining to the I and P pictures before coding and storing them in the respective buffers. Subsequently, the stored data are decoded, decompressed and upsampled for reconstructing blocks of pels to be sent to a macroblock-to-raster scan conversion circuit.

    Abstract translation: MPEG解码器的视频存储器必需实现所述I，P的减压，因此可选地，所述B图像雅丁给MPEG压缩算法的，并要求在respectivement MPEG解压缩数据的所述视频存储器组织respectivement缓冲器中的存储，可 通过子采样和再压缩gemäß被动态地减少到至少关于所述I和P图像的编码数据，并在缓冲器respectivement存储它们之前一个ADPCM算法。 随后，将存储的数据进行解码，解压缩并上采样用于重构象素块将被发送到一个宏数据块到光栅的扫描变换电路。

    Process for the fabrication of integrated circuits with contacts self-aligned to active areas
    40.
    发明公开
    Process for the fabrication of integrated circuits with contacts self-aligned to active areas 失效
    一种用于生产集成电路的工艺具有自对准于有源区的接触

    公开(公告)号：EP0817247A1

    公开(公告)日：1998-01-07

    申请号：EP96830362.8

    申请日：1996-06-26

    Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

    Inventor： Moroni, Maurizio

    IPC: H01L21/265 ,  H01L21/285

    CPC classification number: H01L21/28512 ,  H01L21/26586

    Abstract: A process for the manufacturing of integrated circuits provides for forming contacts between a conductive material layer (5) and first doped regions (4) of a semiconductor substrate (2) in a self-aligned manner to edges of an insulating material layer (1) which defines active areas (3) of the integrated circuit wherein the doped regions (4) are formed, and second doped regions (8) of the same conductivity type as the first doped regions (4) under the first doped regions (4), the second doped regions (8) extending partially under the edges of the insulating material layer (1) to prevent short-circuits between the conductive material layer (5) and the semiconductor substrate (2). The second doped regions (8) are formed by means of implantation of dopants along directions slanted with respect to an orthogonal direction to a surface of the semiconductor substrate (2) at angles and with an energy sufficiently high to make the dopants penetrate in the semiconductor material deeper than the first doped regions (4) and under the edges of the insulating material layer (1).

    Abstract translation: 一种用于制造集成电路的方法提供了形成导电材料层之间的接触（5）和第一掺杂区（4）的半导体的基板（2）以自对准的方式在绝缘材料层的边缘（1） 限定有源区（3）worin掺杂区的集成电路（4）的形成，和第二掺杂区（8）相同的导电类型与第一掺杂区下的第一掺杂区（4）（4） 第二掺杂区（8）的绝缘材料层的边缘下面部分地延伸（1）以防止导电材料层（5）和（2）的半导体衬底之间的短路。 第二掺杂区（8）是由掺杂剂的注入的方式沿成角度在正交方向相对于倾斜，以向所述半导体基板（2）的表面的方向和与能量高到足以使掺杂剂在半导体穿透FORMED 材料比所述第一掺杂区更深（4）和下绝缘材料层的边缘（1）。

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