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    CONFIGURABLE LOGIC ARRAY
    33.
    发明专利
    CONFIGURABLE LOGIC ARRAY 失效

    公开(公告)号：JPH03132212A

    公开(公告)日：1991-06-05

    申请号：JP20109290

    申请日：1990-07-27

    Applicant: XILINX INC

    Inventor： ROSU EICHI FURIIMAN ,  HANGUUCHIENGU SHII

    IPC: H03K19/173 ,  H03K19/177

    Abstract: PURPOSE: To change one part of the set memory cell of a block in the operation by providing a means for setting each configurable logical block, and a means for operating writing in a memory cell. CONSTITUTION: In a configurable logic array, a function generator F1.1 constitutes a multiplexer for reading one of memory cells M1-M13 in response to an address applied to 4 input lines F1-F4. Then, when two way loads are available for a static memory cell, data can be written in the memory cells M1-M13 after the array is set or when it is being set, and a certain memory cell of each logic block in the array can be separately used for a programmed logic. Thus, data can be changed for each table by the control of the logic programmed in the array.

    PROGRAMMABLE LOGIC DEVICE
    36.
    发明专利
    PROGRAMMABLE LOGIC DEVICE 失效

    公开(公告)号：JPH11317659A

    公开(公告)日：1999-11-16

    申请号：JP6237499

    申请日：1999-03-09

    Applicant: XILINX INC

    Inventor： CARTER WILLIAM S ,  FREEMAN ROSS H

    IPC: H01L21/82 ,  H01L27/118 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177 ,  H03K19/20

    Abstract: PROBLEM TO BE SOLVED: To provide a programmable logic device which is formed on an integrated circuit chip, where a user can easily realize a desired logical function by programming. SOLUTION: Plural pieces of logical elements(LE), which respectively contain an input lead (in) and an output lead (out), are provided and a desired logical function is realized by making each logical element a desired form. A group of mutual connection lines (L) which connect among logical elements is provided, and also plural pieces of input/output ports (I/O) are provided. A programmable connecting means which mutually connects a group of mutual connection lines, connects the group of mutual connection lines to the input lead or the output lead of a selected logical element and also selectively connects the group of mutual connection lines to an input/output port by programming is provided.

    TIME-MULTIPLEXED WRITE ENABLED LOGIC CIRCUIT
    37.
    发明专利
    TIME-MULTIPLEXED WRITE ENABLED LOGIC CIRCUIT 失效

    公开(公告)号：JPH09181599A

    公开(公告)日：1997-07-11

    申请号：JP21752796

    申请日：1996-08-19

    Applicant: XILINX INC

    Inventor： SUTEFUAN EMU TORIMUBAAGAA ,  RICHIYAADO EI KAABERII ,  ROBAATO ANDAASU JIYONSON ,  JIENIFUAA UON

    IPC: G11C11/401 ,  G06F15/78 ,  G06F17/50 ,  H03K19/173 ,  H03K19/177

    Abstract: PROBLEM TO BE SOLVED: To respecify the formats of a format specification enabled logic block and a matrix with a programmable route by preparing plural programmable logic elements and including plural memory cells for specifying a combination element format and an order logic element format in the logic elements. SOLUTION: A bit group 200 has eight memory cells MC0 to MC7 and each memory cell MC has a latch 201 and a selecting transistor(TR) 202 related to the latch 201. The memory cells MC0 to MC7 are connected to a common bit line 203 for supplying a signal to a latch 204 to be driven by a clock. All configuration bits (e.g. a 3rd configuration bit stored in a latch 2012 by the memory cell MC2) on the same position of different bit groups are included in a single slice of a memory and correspond to the single configuration (format) of an array.

    HIGH-SPEED CARRY CIRCUIT
    39.
    发明专利
    HIGH-SPEED CARRY CIRCUIT 失效

    公开(公告)号：JPH08110853A

    公开(公告)日：1996-04-30

    申请号：JP26637495

    申请日：1995-09-20

    Applicant: XILINX INC

    Inventor： BAANAADO JIEI NIYUU ,  KERII EMU PIAASU

    IPC: G06F7/38 ,  G06F7/00 ,  G06F7/50 ,  G06F7/503 ,  G06F7/506 ,  G06F7/507 ,  G06F7/57 ,  H03K19/173 ,  H03K19/177

    Abstract: PROBLEM TO BE SOLVED: To provide a programmable logic circuit equipped with a circuit which has a logic block having flexibility in circuit configuration and implements high-speed carry logic. SOLUTION: A programmable logic device in which a plurality of blocks of combinational function generators and storing elements are connected to each other in a programmable interconnecting structure is frequently used for arithmetic operation using carry function generating logic. When processing of many bits is required, a carry function is usually delayed remarkably and a large number of additional elements is required for obtaining results at a high speed. Therefore, hardware exclusively used for executing the carry function at a high speed with the smallest number of elements is provided in a logic block. This circuit is provided with an additional circuit so that the hardware for the high-speed carry function can implement the other conventional functions.

    SOFT WAKE-UP OUTPUT BUFFER
    40.
    发明专利
    SOFT WAKE-UP OUTPUT BUFFER 失效

    公开(公告)号：JPH0795043A

    公开(公告)日：1995-04-07

    申请号：JP3780394

    申请日：1994-02-11

    Applicant: XILINX INC

    Inventor： KERII EMU PIASU ,  CHIYAARUZU AARU ERIKUSON

    IPC: H03K19/173 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175

    Abstract: PURPOSE: To minimize the fluctuation of the potential of a ground line inside a device by controlling the transition state, response speed and through rate control signals of a buffer for outputting signals corresponding to input signals by respective control signals. CONSTITUTION: Logic high/low are defined as H/L, signals GTSB and DONE are both H, a NAND gate U0 turns the signals A to L, a transistor 27 is turned OFF, TSM signals are H and an OR gate U4 turns the signals T to L. By H signals C for which a delay circuit U2 delays the H signals B outputted by an inverter U1 by the L signals A of the time T1 for the time Td and the H signals SRM, an AND gate U3 outputs the H signals D. The signals D are the through rate control signals F/S', the signals 36 and A of input are L and a buffer 21 and an input/output pad 23 are shifted from H→L at a low-speed response mode from the time T1 until cancellation at the time T2. Thus, the fluctuation of the potential of the ground line inside the device is minimized.

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