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公开(公告)号：KR101341984B1
公开(公告)日：2013-12-16
申请号：KR1020120027729
申请日：2012-03-19
Applicant: 고려대학교 산학협력단
Abstract: 본발명은복소수행렬을기븐스회전법(Givens rotation) 기반으로 QR 분해하는방법에있어서, (a) 상기복소수행렬의요소들을실수부와허수부로분리하여중간행렬을생성하는단계; (b) 상기중간행렬에서서로독립적으로연산가능한부분행렬을하나이상선택하는단계; (c) 상기선택된하나이상의부분행렬을병렬처리하고, 연산결과를반영하여상기중간행렬을갱신하는단계; 및 (d) 상기중간행렬이상삼각행렬(upper triangular matrix)이될 때까지상기 (b) 내지 (c) 단계를반복하는단계;를포함하는 QR 분해하는방법을제공한다.
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公开(公告)号：KR1020130106089A
公开(公告)日：2013-09-27
申请号：KR1020120027729
申请日：2012-03-19
Applicant: 고려대학교 산학협력단
CPC classification number: H04L25/0246 , H04B7/0456 , H04L25/0242 , H04L2025/03426
Abstract: PURPOSE: QR decomposition method can reduce operation time. CONSTITUTION: A medium matrix is generated by separating elements of a complex matrix into real part and imaginary part (S810). In the medium matrix, at least one sub-matrix capable of being independently operated is selected. The selected at least one sub-matrix is processed in parallel (S830). The medium matrix is updated reflecting the operation result. Until the medium matrix becomes an upper triangular matrix, at least one sub-matrix capable of being independently operated is selected in the medium matrix. [Reference numerals] (S810) Medium matrix is generated by separating elements of a complex matrix into real part and imaginary part and inputting them; (S820) In the medium matrix, at least one sub-matrix capable of being independently operated is selected; (S830) The selected at least one sub-matrix is processed in parallel and the medium matrix is updated reflecting the operation result; (S840) It is determined whether the medium matrix becomes an upper triangular matrix; (S850) The medium matrix is outputted as an upper triangular matrix
Abstract translation: 目的：QR分解方法可以减少手术时间。 构成：通过将复数矩阵的元素分成实部和虚部来生成中矩阵（S810）。 在中矩阵中，选择能独立操作的至少一个子矩阵。 所选择的至少一个子矩阵被并行处理（S830）。 更新反映操作结果的中矩阵。 直到中矩阵成为上三角矩阵为止，在中矩阵中选择能独立运行的至少一个子矩阵。 （参考标号）（S810）通过将复数矩阵的元素分成实部和虚部并输入它们来生成中矩阵; （S820）在中矩阵中，选择能够独立操作的至少一个子矩阵; （S830）并行处理所选择的至少一个子矩阵，并更新反映操作结果的中矩阵; （S840）确定中矩阵是否成为上三角矩阵; （S850）中矩阵作为上三角矩阵输出
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公开(公告)号：KR1020120126654A
公开(公告)日：2012-11-21
申请号：KR1020110044634
申请日：2011-05-12
Applicant: 에스케이하이닉스 주식회사 , 고려대학교 산학협력단
IPC: G11C29/42
CPC classification number: G11C29/42 , G06F11/1008 , G11C7/1051 , G11C7/1078 , G11C7/22
Abstract: PURPOSE: A semiconductor system is provided to reduce power consumption by controlling an error correction operation according to errors. CONSTITUTION: A selecting unit(110) outputs a first write data code and a first write correction code or a first read data code and a first read correction code according to a mode signal. An error processing unit(120) generates an output data code by correcting the errors of the input data code and generates an output correction code by encoding the output data code. A distribution unit(130) outputs an output data code and an output correction code as a second write data code and a second write correction code or a second read data code and a second read correction code according to a mode signal. A storage unit(140) stores the second write data code and the second write correction code or outputs the stored value as the first read data code and the first read correction code according to a mode signal. [Reference numerals] (140) Storage unit; (200) Controller; (210) Error correcting circuit; (AA) Semiconductor memory device R/W
Abstract translation: 目的：提供半导体系统，通过根据错误控制纠错操作来降低功耗。 构成：选择单元（110）根据模式信号输出第一写入数据代码和第一写入校正代码或第一读取数据代码和第一读取校正代码。 错误处理单元（120）通过校正输入数据代码的错误来生成输出数据代码，并通过对输出数据代码进行编码来生成输出校正码。 分配单元（130）根据模式信号输出输出数据代码和输出校正代码作为第二写入数据代码和第二写入校正代码或第二读取数据代码和第二读取校正代码。 存储单元（140）存储第二写入数据代码和第二写入校正代码，或者根据模式信号将存储的值作为第一读取数据代码和第一读取校正代码输出。 （附图标记）（140）存储单元; （200）控制器; （210）纠错电路; （AA）半导体存储器R / W
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公开(公告)号：KR102208604B1
公开(公告)日：2021-01-29
申请号：KR1020180171084
申请日：2018-12-27
Applicant: 고려대학교 산학협력단
Abstract: 본출원의일 실시예에따르는프로세싱인 메모리는적어도하나의메모리셀에대한이진상태데이터의스위칭확률에기초하여, 시냅스가중치를업데이트하는메모리셀어레이및 기설정된그레이코드에기초하여, 상기적어도하나의메모리셀에대해하나의메모리셀단위로라이트동작을수행하는주변회로부를포함한다.
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Patent Agency Ranking
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公开(公告)号：KR101439815B1
公开(公告)日：2014-09-11
申请号：KR1020130025034
申请日：2013-03-08
Applicant: 고려대학교 산학협력단
IPC: G06F11/10
CPC classification number: H03M13/35 , G06F11/1004 , G06F11/1048 , H03M13/05 , H03M13/152 , H03M13/1545 , H03M13/155 , H03M13/611
Abstract: In the present invention, disclosed are a circuit and a method for correcting the error of a memory. Specially, the method for correcting the error of a memory according to one embodiment of the present invention includes the steps of: adaptively setting a protection range corresponding to an error correction range among unit data to be written in the memory according to an operation voltage of the memory; performing the error correction encoding of protection data which include the most significant bit (MSB) and corresponds to the protection range among the unit data; and writing the unit data in the memory by matching the unit data with parity data which are generated by the error correction encoding. The setting step narrowly sets the protection range according as the operation voltage of the memory becomes low.
Abstract translation: 在本发明中，公开了一种用于校正存储器的误差的电路和方法。 特别地，根据本发明的一个实施例的用于校正存储器的误差的方法包括以下步骤：根据操作电压自适应地设置与写入存储器的单元数据中的纠错范围相对应的保护范围 记忆; 执行包括最高有效位（MSB）的保护数据的纠错编码，并对应于单位数据中的保护范围; 以及通过将单元数据与通过纠错编码生成的奇偶校验数据相匹配来将单元数据写入存储器。 设定步骤根据存储器的工作电压变为低电平来设定保护范围。
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公开(公告)号：KR1020140006402A
公开(公告)日：2014-01-16
申请号：KR1020120073211
申请日：2012-07-05
Applicant: 에스케이하이닉스 주식회사 , 고려대학교 산학협력단
IPC: H03M13/00
CPC classification number: H03M13/353 , H03M13/6337 , H03M13/6508
Abstract: Provided in the present invention is a reconfigurable error correction code device capable of changing a structure driven according to a noise environment; the number of syndrome generators driven according to the size of the noise; the number of error position polynomial generators driven according to the size of the noise; and power consumption for the error correction according to the size of the noise. The reconfigurable error correction code device according to a first aspect of the present invention comprises: a main controller for outputting a selection control signal in correspondence to the number of error correction bits; an encoder controlled by the selection control signal for outputting a code word formed with a data bit and a parity bit by multiplying a generator matrix with an inputted data bit; a syndrome generator controlled by the selection control signal for receiving the code word from a storage part and outputting a syndrome value; a key equation solver controlled by the selection control signal for generating an error position detection coefficient for detecting the error position by using the syndrome value; an error position detector controlled by the selection control signal for outputting the error position detection signal by using the error position detection coefficient; and an error correction part controlled by the selection control signal for correcting the error of the corresponding position by using the error position detection signal.
Abstract translation: 本发明提供一种能够改变根据噪声环境驱动的结构的可重构纠错码装置; 根据噪声大小驱动的综合征发生器数量; 根据噪声大小驱动的误差位置多项式发生器的数量; 和根据噪声大小进行纠错的功耗。 根据本发明的第一方面的可重构纠错码器件包括：主控制器，用于输出与纠错位数相对应的选择控制信号; 由选择控制信号控制的编码器，用于通过将发生器矩阵与输入的数据位相乘来输出由数据位和奇偶校验位形成的代码字; 由选择控制信号控制的校正子发生器，用于从存储部分接收代码字并输出校正子值; 由所述选择控制信号控制的关键方程求解器，用于通过使用所述校正子值产生用于检测所述误差位置的误差位置检测系数; 由选择控制信号控制的误差位置检测器，用于通过使用误差位置检测系数输出误差位置检测信号; 以及由选择控制信号控制的纠错部分，用于通过使用误差位置检测信号来校正相应位置的误差。
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公开(公告)号：KR101217218B1
公开(公告)日：2012-12-31
申请号：KR1020110022706
申请日：2011-03-15
Applicant: 고려대학교 산학협력단
CPC classification number: H01L27/1104 , G09G5/39 , H01L27/0207
Abstract: 본발명에따른영상처리프로세서는, 복수의메모리셀을포함하는단위메모리블록을복수개 포함하는그래픽메모리및 입출력부를통해수신한그래픽데이터의각 비트를상기그래픽메모리의각 메모리셀에저장시키고, 상기그래픽메모리의각 메모리셀에저장된그래픽데이터를독출하여상기입출력부를통해출력시키는제어부를포함하고, 상기복수의메모리셀 중적어도둘 이상의메모리셀의면적은서로상이하고, 상기제어부는상기그래픽데이터의중요도및 상기메모리셀의면적에따라상기그래픽데이터의각 비트를할당하되, 상기메모리셀의면적이넓을수록중요도가큰 그래픽데이터의비트를할당한다. 또한, 본발명에따른그래픽메모리는복수의메모리셀을포함하는단위메모리블록을복수개 포함하되, 상기복수의메모리셀 중적어도둘 이상의메모리셀의면적은서로상이하다.
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公开(公告)号：KR101158548B1
公开(公告)日：2012-07-16
申请号：KR1020100081375
申请日：2010-08-23
Applicant: 고려대학교 산학협력단
Abstract: 본 발명에 따른 코딕 처리를 수행하는 프로세서는, 입력 데이터, 상기 입력 데이터에 대한 보수(補數), 상기 입력 데이터의 쉬프트 값 및 상기 입력 데이터의 쉬프트 값에 대한 보수 중 하나 이상에 대하여 벡터링 처리를 각각 수행하는 N개(N은 자연수)의 벡터링 처리부 및 로테이션 입력 데이터, 로테이션 입력 데이터에 대한 보수, 로테이션 입력 데이터의 쉬프트 값 및 상기 로테이션 입력 데이터의 쉬프트 값에 대한 보수에 대하여 로테이션 처리를 수행하여 상기 입력 데이터에 대한 삼각함수 출력값을 출력하는 로테이션 처리부를 포함하되, 상기 벡터링 처리부 및 로테이션 처리부는 병렬 접속되어 각각의 벡터링 처리 또는 로테이션 처리를 수행하고, 상기 로테이션 처리부는 상기 입력 데이터의 부호값 및 상기 N개의 벡터링 처리부의 출력 데이터의 부호값에 기초하여 상기 로테이션 처리의 출력값 중 상기 삼각함수 출력값을 선택하여 출력한다.
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