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公开(公告)号：KR1020050001159A
公开(公告)日：2005-01-06
申请号：KR1020030042730
申请日：2003-06-27
Applicant: 삼성전자주식회사
IPC: H01L23/12
CPC classification number: H01L25/0657 , H01L21/563 , H01L23/49575 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/78 , H01L2224/05568 , H01L2224/05573 , H01L2224/11 , H01L2224/1134 , H01L2224/13 , H01L2224/1308 , H01L2224/131 , H01L2224/13144 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48465 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/78301 , H01L2225/06562 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/18161 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2224/13099 , H01L2924/00 , H01L2224/48227 , H01L2924/00012 , H01L2224/05599
Abstract: PURPOSE: A multichip package with a plurality of flip chips is provided to achieve an improved operation speed and a reduced thickness in forming a large capacity package by stacking a plurality of chips on a PCB(printed circuit board). CONSTITUTION: A PCB has a flat substrate(51) and a plurality of interconnections formed on the front surface of the substrate. A plurality of flip chips are sequentially formed on the front surface of the PCB, including a lowest flip chip(53) with pads(55) facing the PCB and at least one upper flip chip(71). The first group of bumps(57) are interposed between the pads of the lowest flip chip and the first group of interconnections(61a) among the plurality of interconnections. The second group of bumps(75) are interposed between the pads(73) of the at least one upper flip chip and the second group of interconnections(61b) among the plurality of interconnections.
Abstract translation: 目的：提供具有多个倒装芯片的多芯片封装，以通过在PCB（印刷电路板）上堆叠多个芯片来实现形成大容量封装的改进的操作速度和减小的厚度。 构成：PCB具有平坦的基板（51）和形成在基板的前表面上的多个互连。 多个倒装芯片顺序地形成在PCB的前表面上，包括具有面向PCB的焊盘（55）和至少一个上倒装芯片（71）的最低倒装芯片（53）。 第一组突起（57）插入在多个互连中的最低倒装芯片的焊盘和第一组互连（61a）之间。 第二组突起（75）插入在多个互连中的至少一个上倒装芯片的焊盘（73）和第二组互连（61b）之间。
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公开(公告)号：KR100445072B1
公开(公告)日：2004-08-21
申请号：KR1020010043446
申请日：2001-07-19
Applicant: 삼성전자주식회사
IPC: H01L23/495
CPC classification number: H01L23/3107 , H01L21/4832 , H01L23/49548 , H01L24/48 , H01L24/49 , H01L2224/05553 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2224/85001 , H01L2224/85411 , H01L2224/85444 , H01L2224/85464 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/10161 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
Abstract: 본 발명은 리드 프레임을 이용한 범프 칩 캐리어(BCC; Bumped Chip Carrier) 패키지 및 그 제조 방법에 관한 것으로, 범프 칩 캐리어 패키지가 제조된 이후에 진행되는 신뢰성 테스트에서 외부접속단자가 손상되는 것을 방지하기 위해서, (a) 칩 실장 영역과, 상기 칩 실장 영역의 외측에 돌출된 복수개의 내부접속단자를 갖는 리드 프레임을 제공하는 단계와; (b) 복수개의 전극 패드를 갖는 반도체 칩을 상기 칩 실장 영역에 부착하는 단계와; (c) 상기 반도체 칩의 전극 패드와 상기 내부접속단자를 본딩 와이어로 전기적으로 연결하는 단계와; (d) 상기 리드 프레임 위의 반도체 칩, 본딩 와이어 및 내부접속단자를 액상의 성형수지로 봉합하여 수지 봉합부를 형성하는 단계; 및 (e) 상기 내부접속단자 아래의 부분만 만기고 상기 리드 프레임을 제거하여 외부접속단자를 형성하는 단계를 포함하는 것을 특징으로 하는 리드 프레임을 이용한 범프 칩 캐리어 패키지의 제조 방법과, 그 제조 방법으로 제조된 범프 칩 캐리어 패키지를 제공한다.
Abstract translation: 根据本发明的改进的凸点式芯片载体（BCC）封装包括封装附着的半导体集成电路（IC）的树脂模制引线框架和将IC上的多个接触焊盘附接到相关联的多个互连线 焊接覆盖的外部接触端子集成在引线框架中。 通过一体化处理外部接触端子，可以使用单线接合工艺来固定接合线。 用于制造BCC封装的方法优选地包括双重光刻胶图案化工艺，伴随着双湿蚀刻工艺，以产生多个具有改进的接触端子和封装树脂模具之间的接合的高度可靠的外部接触端子。
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公开(公告)号：KR1020040038462A
公开(公告)日：2004-05-08
申请号：KR1020020067421
申请日：2002-11-01
Applicant: 삼성전자주식회사
IPC: H01L23/12
CPC classification number: H01L2224/48247 , H01L2224/48465 , H01L2924/00
Abstract: PURPOSE: A multi chip package is provided to reduce the fabricating cost and time by eliminating the necessity that an active surface of one semiconductor chip among stacked semiconductor chips should be a mirror image of an active surface of another semiconductor chip. CONSTITUTION: Plural bonding pads are formed on the active surface of the first semiconductor chip(21). Plural bonding pads are formed on the active surface of the second semiconductor chip(22). The first and second semiconductor chips are attached to a die pad(24). Inner leads(27) are separated from the die pad. Bonding wires(29) electrically connect the bonding pads(23) of the first and second semiconductor chips with the inner leads. A package body(201) encapsulates the die pad, the first and second semiconductor chips, the inner leads and the bonding wires. Outer leads(28) are built in the inner leads, protruding to the outside of the package body. The first and second semiconductor chips are the same. The bonding pads in the first and second semiconductor chips are of an edge pad structure. The active surface of the first semiconductor chip is attached to the lower portion of the die pad and the inactive surface of the semiconductor chip is attached to the upper portion of the die pad, so that the active surfaces face the same direction. When the active surface of the first semiconductor chip is attached to the lower portion of the die pad, the bonding pads on the active surface of the first semiconductor chip is formed near the die pad.
Abstract translation: 目的：提供一种多芯片封装，通过消除层叠的半导体芯片中的一个半导体芯片的有源表面应该是另一半导体芯片的有源表面的镜像的必要性来减少制造成本和时间。 构成：在第一半导体芯片（21）的有源表面上形成多个接合焊盘。 多个接合焊盘形成在第二半导体芯片（22）的有源表面上。 第一和第二半导体芯片附接到管芯焊盘（24）。 内引线（27）与管芯焊盘分离。 接合线（29）将第一和第二半导体芯片的接合焊盘（23）与内引线电连接。 封装体（201）封装管芯焊盘，第一和第二半导体芯片，内部引线和接合线。 外引线（28）内置在内引线上，突出到封装体的外部。 第一和第二半导体芯片是相同的。 第一和第二半导体芯片中的接合焊盘具有边缘焊盘结构。 第一半导体芯片的有源表面附接到芯片焊盘的下部，并且半导体芯片的非活动表面附接到芯片焊盘的上部，使得有源表面面向相同的方向。 当第一半导体芯片的有源表面附接到芯片焊盘的下部时，第一半导体芯片的有源表面上的焊盘形成在芯片焊盘附近。
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公开(公告)号：KR1020020068709A
公开(公告)日：2002-08-28
申请号：KR1020010008936
申请日：2001-02-22
Applicant: 삼성전자주식회사
IPC: H01L23/12
CPC classification number: H01L21/568 , H01L21/6835 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/86 , H01L25/50 , H01L2224/32245 , H01L2224/451 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/181 , H01L2924/00 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012
Abstract: PURPOSE: A dual die package and a method for fabricating the same are provided to reduce total thickness of the dual die package and prevent a damage of a conductive metallic wire for wire bonding. CONSTITUTION: The first semiconductor chip(11) and the second semiconductor chip(13) are mounted in a dual die package. The first semiconductor chip(11) and the second semiconductor chip(13) are adhered to each other by an adhesive(25). A plurality of leads(23) are formed around the first semiconductor chip(11) and the second semiconductor chip(13). A plurality of metallic wires(27,28) are connected with electrode pads(12,14), respectively. The first semiconductor chip(11) and the second semiconductor chip(13) are electrically with the leads(23). The first semiconductor chip(11) and the metallic wire(27) are sealed by the first sealing portion(33). The second semiconductor chip(13) and the metallic wire(28) are sealed by the first sealing portion(35).
Abstract translation: 目的：提供双管芯封装及其制造方法，以减少双管芯封装的总厚度并防止导线金属线损坏引线接合。 构成：将第一半导体芯片（11）和第二半导体芯片（13）安装在双模封装中。 第一半导体芯片（11）和第二半导体芯片（13）通过粘合剂（25）彼此粘合。 多个引线（23）围绕第一半导体芯片（11）和第二半导体芯片（13）形成。 多个金属线（27,28）分别与电极焊盘（12,14）连接。 第一半导体芯片（11）和第二半导体芯片（13）与引线（23）电连接。 第一半导体芯片（11）和金属线（27）由第一密封部（33）密封。 第二半导体芯片（13）和金属线（28）由第一密封部（35）密封。
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公开(公告)号：KR1020020045674A
公开(公告)日：2002-06-20
申请号：KR1020000074945
申请日：2000-12-09
Applicant: 삼성전자주식회사
IPC: H01L23/28
CPC classification number: H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/92247 , H01L2924/181 , H01L2924/00014 , H01L2924/00012
Abstract: PURPOSE: A method for fabricating a dual die package using tape is provided to improve reliability of a package, by preventing a chip and a conductive metal wire from being damaged by various causes such as a mechanical contact with process equipment. CONSTITUTION: Tape(41) is attached to a surface of a lead frame(20) on which a semiconductor chip is mounted. The first semiconductor chip(11) is mounted on the lead frame. The first semiconductor chip and the lead frame are bonded by a conductive metal wire(27). The first semiconductor chip, a conductive metal wire and a junction region with the conductive metal wire are encapsulated. The tape attached to the lead frame is eliminated. The second semiconductor chip is mounted on a surface opposite to the surface on which the first semiconductor chip of the lead frame is mounted. The second semiconductor chip and the lead frame are bonded by a conductive metal wire. The second semiconductor chip, the conductive metal wire and a junction region with the conductive metal wire are encapsulated.
Abstract translation: 目的：提供一种用于制造使用带的双模包装的方法，以通过防止芯片和导电金属丝被诸如与工艺设备的机械接触的各种原因而损坏来提高包装的可靠性。 构成：胶带（41）附接到其上安装有半导体芯片的引线框架（20）的表面。 第一半导体芯片（11）安装在引线框架上。 第一半导体芯片和引线框架由导电金属线（27）接合。 第一半导体芯片，导电金属线和与导电金属线的接合区域被封装。 附着在引线框架上的磁带被消除。 第二半导体芯片安装在与引线框架的第一半导体芯片安装在其上的表面相对的表面上。 第二半导体芯片和引线框架通过导电金属线接合。 第二半导体芯片，导电金属线和与导电金属线的接合区域被封装。
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Patent Agency Ranking
公开(公告)号：KR1020000039057A
公开(公告)日：2000-07-05
申请号：KR1019980054262
申请日：1998-12-10
Applicant: 삼성전자주식회사
IPC: H01L23/50
Abstract: PURPOSE: A ball grid package is provided to employ any chips of various size in either structure of fan-in or fan-out. CONSTITUTION: A ball grid array package includes a chip(10) attached under a printed circuit board(12) by an elastomer(17) such as silicone. While the chip(10) has balls(20) centrally formed on a top surface thereof, the printed circuit board(12) has a window(18) centrally formed therein and exposing the balls(20). Through the window(18), the balls(20) are connected with circuit patterns on the printed circuit board(12) by wires(22). A mold layer(16) covers all of the wires(22), the window(18) and balls(20), and another mold layer(16) covers sides of the chip(10) and the bottom of the board(12). A plurality of solder balls(14) are formed on the top of the board(12) and then connected with the circuit patterns on the board(12), surrounding the mold layer(16) on the chip(10). Both mold layers(16) are formed in a mold die having top and bottom cavities by a conventional transfer molding method.
Abstract translation: 目的：提供球栅包装，以在任何风扇或扇出的结构中采用各种尺寸的任何芯片。 构成：球栅阵列封装包括通过弹性体（17）如硅树脂附着在印刷电路板（12）下面的芯片（10）。 当芯片（10）在其顶表面上居中形成有球（20）时，印刷电路板（12）具有中心地形成在其中并露出球（20）的窗（18）。 通过窗口（18），球（20）通过电线（22）与印刷电路板（12）上的电路图案相连。 模具层（16）覆盖所有的导线（22），窗口（18）和滚珠（20），而另一模具层（16）覆盖芯片（10）的侧面和板（12）的底部， 。 多个焊球（14）形成在板（12）的顶部上，然后与板（12）上的电路图案相连，围绕芯片（10）上的模层（16）。 两个模具层（16）通过常规的传递模塑方法形成在具有顶部和底部空腔的模具模具中。
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公开(公告)号：KR102250791B1
公开(公告)日：2021-05-11
申请号：KR1020140115075
申请日：2014-09-01
Applicant: 삼성전자주식회사
Abstract: 본발명의다양한실시예에따른네트워크접속관리방법은, 적어도하나의어플리케이션의네트워크연결을요청하는동작과, 상기어플리케이션의적어도하나의속성정보를확인하는동작과, 상기적어도하나의속성정보를기반으로상기어플리케이션에대응하는 APN을결정하는동작과, 상기결정된 APN(access point name)를이용하여네트워크에상기어플리케이션의데이터를송수신하는동작을포함할수 있다.
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公开(公告)号：KR1020170067354A
公开(公告)日：2017-06-16
申请号：KR1020150173929
申请日：2015-12-08
Applicant: 삼성전자주식회사
CPC classification number: G06F8/61 , G06F8/38 , G06F8/65 , H04L63/0815 , H04L63/108 , H04L67/26 , H04W4/50
Abstract: 일실시예에따른전자장치는, 외부장치와통신하기위한통신회로, 제1 시구간에대응하는제1 설정데이터를저장하기위한메모리, 및상기통신회로및 상기메모리와기능적을연결된프로세서를포함할수 있다. 상기프로세서는, 지정된시각에이르면, 제2 시구간에대응하는제2 설정데이터를상기통신회로를통해상기외부장치로부터수신하고, 사용자의로그인또는로그아웃상태에따라서, 상기제1 설정데이터의적어도일부를삭제하고, 및상기제2 설정데이터를상기전자장치에적용하도록설정될수 있다. 이외에도명세서를통해파악되는다양한실시예가가능하다.
Abstract translation: 根据一个实施例的电子器件，它可以包含在外部装置和通信电路，存储器，通信电路，以及耦合到所述存储器和功能，以存储对应于所述第一时间段之间用于通信的第一组数据的一个处理器 。 所述处理器达到给定的时间，根据第二设定数据，从外部装置接收到的，并在用户登录或通过所述第二时间间隔之间对应于，至少所述第一组数据的一个部分中的通信电路的状态出 并将第二设置数据应用于电子设备。 通过说明书已知的各种实施例也是可能的。
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