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公开(公告)号：WO2016036110A1
公开(公告)日：2016-03-10
申请号：PCT/KR2015/009192
申请日：2015-09-01
Applicant: 삼성전자주식회사
Abstract: 본 발명의 다양한 실시 예에 따른 네트워크 접속 관리 방법은, 적어도 하나의 어플리케이션의 네트워크 연결을 요청하는 동작과, 상기 어플리케이션의 적어도 하나의 속성 정보를 확인하는 동작과, 상기 적어도 하나의 속성 정보를 기반으로 상기 어플리케이션에 대응하는 APN을 결정하는 동작과, 상기 결정된 APN(access point name)를 이용하여 네트워크에 상기 어플리케이션의 데이터를 송수신하는 동작을 포함할 수 있다.
Abstract translation: 根据本发明的各种实施例的网络接入管理方法可以包括以下步骤：请求至少一个应用的网络连接; 检查应用程序的至少一个属性信息; 基于所述至少一个属性信息确定与所述应用相对应的接入点名称（APN）; 以及通过使用确定的APN通过网络发送和接收应用的数据。
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公开(公告)号：KR1020160026377A
公开(公告)日：2016-03-09
申请号：KR1020140115075
申请日：2014-09-01
Applicant: 삼성전자주식회사
Abstract: 본발명의다양한실시예에따른네트워크접속관리방법은, 적어도하나의어플리케이션의네트워크연결을요청하는동작과, 상기어플리케이션의적어도하나의속성정보를확인하는동작과, 상기적어도하나의속성정보를기반으로상기어플리케이션에대응하는 APN을결정하는동작과, 상기결정된 APN(access point name)를이용하여네트워크에상기어플리케이션의데이터를송수신하는동작을포함할수 있다.
Abstract translation: 根据本发明的各种实施例，一种用于管理网络接入的方法可以包括以下操作：请求至少一个应用的网络连接; 识别所述应用的至少一个属性信息项; 基于所述至少属性信息项确定与所述应用相对应的接入点名称（APN）; 通过使用确定的APN向网络和从网络发送和接收应用的数据。 根据本发明的各种实施例，可以从电子设备识别每个应用程序应该发送数据的网络，通过使用识别的信息可以将正在使用的应用的数据发送到对应的网络。 因此，可以在移动运营商的侧面高效地收集计费目标数据。
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公开(公告)号：KR100604840B1
公开(公告)日：2006-07-28
申请号：KR1020040016414
申请日：2004-03-11
Applicant: 삼성전자주식회사
IPC: H01L21/60
CPC classification number: H01L24/85 , H01L24/03 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L25/0657 , H01L2224/03 , H01L2224/0401 , H01L2224/04042 , H01L2224/05599 , H01L2224/1134 , H01L2224/32145 , H01L2224/45015 , H01L2224/45144 , H01L2224/48011 , H01L2224/48091 , H01L2224/48227 , H01L2224/48451 , H01L2224/48465 , H01L2224/48471 , H01L2224/48479 , H01L2224/48599 , H01L2224/4903 , H01L2224/49051 , H01L2224/78301 , H01L2224/85051 , H01L2224/8518 , H01L2224/85186 , H01L2224/85986 , H01L2225/0651 , H01L2924/00013 , H01L2924/00014 , H01L2924/01006 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/181 , H01L2924/19107 , H01L2924/20752 , H01L2924/20753 , H01L2924/20651 , H01L2224/13099 , H01L2924/00 , H01L2924/00015 , H01L2224/4554 , H01L2224/85399
Abstract: 미세 피치 범프(fine pitch bump)에의 리버스 와이어 본딩(reverse wire bonding) 방법 및 이에 의한 와이어 본드 구조체를 제공한다. 본 발명의 일 관점에 따른 와이어 본딩 방법은, 적어도 제1패드를 가지는 캐리어(carrier) 및 제1패드에 비해 작은 크기의 제2패드를 가지는 반도체 칩을 제공한다. 제2패드 상에 도전성의 스터드 범프(stud bump)를 형성한다. 제1패드 상에 볼 본딩 형태(ball bonding fashion)의 본딩에 의해 스터드 범프에 비해 큰 직경을 가지게 형성된 돌기를 통해 제1패드에 전기적으로 연결되고 돌기에서 스터드 범프 상으로 연장되고 스터드 범프에 스티치 본딩 형태(stitch bonding fashion)로 본딩되어 제2패드에 전기적으로 연결되는 도전성의 본딩 와이어를 형성한다. 이때, 스터드 범프(stud bump)는 본딩 와이어에 비해 상대적으로 작은 직경을 가지는 와이어를 사용하여 볼 본딩 형태(ball bonding fashion)의 본딩에 의해 형성되는 돌기로서 제2패드 상에 부착되게 형성될 수 있다.
미세 패드, 리버스 본딩, 스터드 범프, 스위핑, 와이어 휨-
公开(公告)号：KR1020060029925A
公开(公告)日：2006-04-07
申请号：KR1020040078790
申请日：2004-10-04
Applicant: 삼성전자주식회사
CPC classification number: H01L25/50 , H01L24/32 , H01L24/73 , H01L25/0657 , H01L2224/1134 , H01L2224/1308 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2224/78301 , H01L2224/83136 , H01L2225/0651 , H01L2225/06555 , H01L2225/06562 , H01L2225/06575 , H01L2924/01006 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2924/00014 , H01L2924/00 , H01L2924/3512 , H01L2924/00012
Abstract: A multi-chip package and method for manufacturing are disclosed. The multi-chip package may include a substrate, a lower semiconductor chip mounted on the substrate, a first electrical connection for electrically connecting the substrate and the lower semiconductor chip, an upper semiconductor chip attached to the lower semiconductor chip and having overhang portions, and at least one bump interposed between the substrate and the overhang portions. The at least one bump may support the overhang portions and may be formed when the first electrical connection is formed.
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公开(公告)号：KR1020040056688A
公开(公告)日：2004-07-01
申请号：KR1020020083229
申请日：2002-12-24
Applicant: 삼성전자주식회사
Inventor： 강인구
IPC: H01L21/027
Abstract: PURPOSE: A chemical supplying apparatus is provided to efficiently control leakage water and temperature by using a heat pipe instead of a constant temperature water, and to precisely control the temperature of the chemicals injected to a wafer by installing the heat pipe in a position most adjacent to a nozzle and by directly controlling the temperature of the chemicals of a chemical line. CONSTITUTION: Chemicals are supplied from a chemical storing tank(11) that is connected to a unit apparatus(20) for performing a process for fabricating a specific semiconductor by a chemical line(13). The heat pipe(17) for generating heat to the chemical line is installed in the chemical supplying apparatus. A temperature control unit(15) for controlling the temperature of the heat pipe is connected to the heat pipe.
Abstract translation: 目的：提供一种化学品供应装置，通过使用热管代替恒温水来有效地控制泄漏水和温度，并通过将热管安装在最相邻的位置来精确控制注入到晶片的化学品的温度 并直接控制化学品的化学品的温度。 构成：化学品从连接到单元装置（20）的化学品储存罐（11）供应，用于通过化学品管线（13）进行用于制造特定半导体的工艺。 用于向化学品生产线发热的热管（17）安装在化学品供应装置中。 用于控制热管的温度的温度控制单元（15）连接到热管。
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Patent Agency Ranking
公开(公告)号：KR1020030075860A
公开(公告)日：2003-09-26
申请号：KR1020020015329
申请日：2002-03-21
Applicant: 삼성전자주식회사
IPC: H01L23/12
CPC classification number: H01L24/85 , H01L24/29 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/05599 , H01L2224/2919 , H01L2224/2929 , H01L2224/29339 , H01L2224/30505 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48465 , H01L2224/48471 , H01L2224/48479 , H01L2224/73265 , H01L2224/83139 , H01L2224/85051 , H01L2224/85186 , H01L2224/85399 , H01L2224/85986 , H01L2224/92247 , H01L2225/0651 , H01L2225/06513 , H01L2225/06575 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01047 , H01L2924/07802 , H01L2924/12041 , H01L2924/14 , H01L2924/15787 , H01L2924/0715 , H01L2924/0665 , H01L2224/78 , H01L2224/45099 , H01L2924/00 , H01L2924/00012 , H01L2224/4554
Abstract: PURPOSE: A semiconductor chip stacked structure and a method for stacking a semiconductor chip are provided to be capable of minimizing the height of the semiconductor chip stacked structure regardless of the size of the first and second chip. CONSTITUTION: A semiconductor chip stacked structure(30) is provided with a substrate(31) including a chip adhering region(32a) and a line pattern(33), the first chip(34) having a plurality of first electrode pads(35), attached to the chip adhering region, the first metal bump(37) formed at each first electrode pad, the first bonding wire(38) for electrically connecting the first metal bump of the first chip to the substrate, an insulating liquid adhesive(39) coated at the active surface of the first chip, the second chip(40) stacked on the first chip using the insulating liquid adhesive, and the second bonding wire(44) for electrically connecting the second electrode pad of the second chip to the line pattern of the substrate.
Abstract translation: 目的：提供半导体芯片堆叠结构和堆叠半导体芯片的方法，以便能够使半导体芯片堆叠结构的高度最小化，而与第一和第二芯片的尺寸无关。 构成：半导体芯片堆叠结构（30）具有包括芯片接合区域（32a）和线路图案（33）的基板（31），第一芯片（34）具有多个第一电极焊盘（35） 在第一电极焊盘上形成的第一金属凸块（37），将第一芯片的第一金属凸块与基板电连接的第一接合线（38），绝缘液体粘合剂（39） ），使用绝缘液体粘合剂堆叠在第一芯片上的第二芯片（40）和用于将第二芯片的第二电极焊盘电连接到线路的第二接合线（44） 衬底图案。
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公开(公告)号：KR1020010056903A
公开(公告)日：2001-07-04
申请号：KR1019990058575
申请日：1999-12-17
Applicant: 삼성전자주식회사
IPC: H01L23/28
CPC classification number: H01L24/97 , H01L24/94 , H01L2224/16145 , H01L2224/16225 , H01L2224/1703 , H01L2224/94 , H01L2224/97 , H01L2924/15311 , H01L2224/81
Abstract: PURPOSE: A chip scale stack chip package and a manufacturing method thereof are provided to attain a high integration with reduced size and weight while having a plurality of chips. CONSTITUTION: The package(50) includes the first and second chips(12,32). The first chip(12) has the first insulating layer covering an active surface thereof except electrode pads, redistribution metal lines connected to the electrode pads and then extended over the first insulating layer, the second insulating layer covering the metal lines but having windows exposing parts of each metal line, and the first terminals(26) of bump shape formed in the outer windows and connected to the metal lines. The second chip(32) has the second terminals(37) of bump shape formed on electrode pads thereof and connected to the metal lines of the first chip(12) through the inner windows of the first chip(12). The second terminals(37) are smaller in height than the first terminals(26). The package(50) further includes a printed circuit board(51) to which the first chip(12) is attached by the first terminals(26), a resin encapsulant(55) filled in a space between the first chip(12) and the circuit board(51), and the third terminals(54) mounted on the circuit board(51) and electrically connected to the first terminals(26).
Abstract translation: 目的：提供一种芯片级堆叠芯片封装及其制造方法，以在具有多个芯片的同时实现尺寸和重量减小的高集成度。 构成：包装（50）包括第一和第二芯片（12,32）。 第一芯片（12）具有覆盖其活性表面的第一绝缘层，除了电极焊盘，再分配金属线连接到电极焊盘，然后在第一绝缘层上延伸，第二绝缘层覆盖金属线，但具有窗口暴露部分 的每个金属线，以及形成在外窗中并连接到金属线的凸起形状的第一端子（26）。 第二芯片（32）具有形成在其电极焊盘上的凸起形状的第二端子（37），并通过第一芯片（12）的内部窗口与第一芯片（12）的金属线连接。 第二端子（37）的高度比第一端子（26）小。 所述封装（50）还包括印刷电路板（51），所述第一芯片（12）由所述第一端子（26）附接到所述印刷电路板（51），树脂密封剂（55）填充在所述第一芯片（12）和 电路板（51）和安装在电路板（51）上并电连接到第一端子（26）的第三端子（54）。
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公开(公告)号：KR1020010002704A
公开(公告)日：2001-01-15
申请号：KR1019990022632
申请日：1999-06-17
Applicant: 삼성전자주식회사
IPC: H01L23/12
CPC classification number: H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/00
Abstract: PURPOSE: A ball grid array package and method thereof is provided to improve reliability of a solder junction and the BGA package by maintaining an adequate distance between the solder and the stud bump. CONSTITUTION: A substrate pad(23) is formed to have a step of a given depth at one side of a substrate body,(21) and a junction pad(27) is formed on an opposite side thereof. A wiring pattern(25) for electrically connecting the substrate pad and the junction pad, and a printed circuit board(20) having a solder layer form on the substrate pad are provided. A semiconductor chip(11) is attached so that each of stud bumps(14) on a plurality of electrode pads(12) formed in an active side with an adhesive means intervened between the printed circuit board, and corresponding substrates pads are separated by the same distance. The stud bump of the semiconductor chip and the substrate pad are joined by melting the solder layer by applying a given atmosphere temperature. Then, the junction portion of the electrode pad in the semiconductor chip and the substrate pad are sealed by shaping resin.
Abstract translation: 目的：提供一种球栅阵列封装及其方法，以通过在焊料和柱状凸起之间保持足够的距离来提高焊接点和BGA封装的可靠性。 构成：衬底焊盘（23）形成为在衬底主体的一侧具有给定深度的步骤，（21），并且在其相对侧上形成接合衬垫（27）。 提供了用于将衬底焊盘和接合焊盘电连接的布线图案（25）和在衬底焊盘上具有焊料层形式的印刷电路板（20）。 安装半导体芯片（11），使得形成在主动侧的多个电极焊盘（12）上的每个螺栓凸块（14）与介于印刷电路板和相应的衬底焊盘之间的粘合装置分隔开， 相同的距离 通过施加给定的气氛温度来熔化焊料层，连接半导体芯片和衬底焊盘的凸块。 然后，通过成型树脂密封半导体芯片中的电极焊盘和衬底焊盘的接合部分。
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公开(公告)号：KR1019990012316A
公开(公告)日：1999-02-25
申请号：KR1019970035665
申请日：1997-07-29
Applicant: 삼성전자주식회사
IPC: H01L21/56
Abstract: 본 발명은 반도체 패키지의 몰딩 금형 장치에 관한 것으로, 리드 프레임의 댐바와 면접하는 클램핑부의 소정 영역에 각각 공기 배기부를 형성함으로써 캐비티내로 에폭시 몰딩 컴파운드가 충진될 때 캐비티내의 공기들이 댐바 부분으로 모이지 않고 댐바와 면접하는 클램핑부의 공기 배기부를 통해 분산 배기되어 반도체 패키지의 몰딩 성형률이 향상되며, 이로 인해 제품의 수율이 향상된다.
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