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公开(公告)号：KR1020100024256A
公开(公告)日：2010-03-05
申请号：KR1020080083025
申请日：2008-08-25
Applicant: 삼성전자주식회사
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/08 , G11C8/08
Abstract: PURPOSE: A non-volatile memory device and a method for operating the same are provided to perform the erase operation of a cell transistor by applying a ground voltage to the control gate and applying a higher voltage than power voltage to a semiconductor substrate. CONSTITUTION: A first and a second strings include memory cell transistors(TM1_1 to TM1_32, TM2_1 to TM2_32) arranged in a row. First word-lines are respectively connected to the gates of memory cell transistors included in the first string. Second word-lines are respectively connected to the gates of memory cell transistors included in the second string. A first dummy cell transistor(TD1) is connected to the memory cell transistor located on one end of the first string. A second dummy cell transistor(TD2) is connected to the memory cell transistor located on one end of the second string. The first dummy word-line is connected to the gate of the first dummy cell transistor. The second dummy word-line is connected to the gate of the second dummy cell transistor.
Abstract translation: 目的：提供一种非易失性存储器件及其操作方法，用于通过向控制栅极施加接地电压并向半导体衬底施加比功率电压更高的电压来执行单元晶体管的擦除操作。 构成：第一和第二串包括排成行的存储单元晶体管（TM1_1至TM1_32，TM2_1至TM2_32）。 第一字线分别连接到包括在第一串中的存储单元晶体管的栅极。 第二字线分别连接到包括在第二串中的存储单元晶体管的栅极。 第一虚拟单元晶体管（TD1）连接到位于第一串的一端的存储单元晶体管。 第二虚设单元晶体管（TD2）连接到位于第二串的一端的存储单元晶体管。 第一虚拟字线连接到第一虚拟单元晶体管的栅极。 第二虚拟字线连接到第二虚拟单元晶体管的栅极。
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公开(公告)号：KR1020100018156A
公开(公告)日：2010-02-17
申请号：KR1020080076798
申请日：2008-08-06
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L27/0688 , H01L25/0657 , H01L27/11526 , H01L27/11529 , H01L27/11551 , H01L27/12 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
Abstract: PURPOSE: A stacked semiconductor device and a method of manufacturing the same are provided to prevent a unit elements from being heated and deteriorating by connecting the top semiconductor pattern with the surface of a single crystalline. CONSTITUTION: A first interlayer insulating film(104) is formed on a single crystalline semiconductor substrate(100). A first contact plug(106) connected through the first interlayer insulating film to the single crystalline semiconductor substrate is formed. A top semiconductor pattern(114) is formed on the first interlayer insulating film while contacting the upper side of the first contact plug. An upper transistor including an impurity region and a gate structure(118) is formed on the top semiconductor pattern. Cell transistors provided as a cell array are offered on the single-crystal semiconductor substrate. The upper transistor has an operating voltage different from the cell transistor.
Abstract translation: 目的：提供叠层半导体器件及其制造方法，以通过将顶部半导体图案与单晶表面连接来防止单元元件被加热和劣化。 构成：在单晶半导体衬底（100）上形成第一层间绝缘膜（104）。 形成通过第一层间绝缘膜连接到单晶半导体衬底的第一接触插头（106）。 顶部半导体图案（114）形成在第一层间绝缘膜上，同时接触第一接触插塞的上侧。 在顶部半导体图案上形成包括杂质区域和栅极结构（118）的上部晶体管。 作为单元阵列提供的单体晶体管被提供在单晶半导体衬底上。 上部晶体管具有与单元晶体管不同的工作电压。
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公开(公告)号：KR1020090123242A
公开(公告)日：2009-12-02
申请号：KR1020080049219
申请日：2008-05-27
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L21/76224 , H01L21/8221 , H01L27/0688 , H01L27/11526 , H01L27/11529 , H01L27/11551 , H01L27/1211 , H01L21/845
Abstract: PURPOSE: A semiconductor device including a driving transistor is provided to reduce a separation distance between a semiconductor pattern and an adjacent semiconductor pattern by arranging the semiconductor pattern in which a driving transistor is formed on an insulation film. CONSTITUTION: An insulation film and a semiconductor film are successively arranged on a substrate. An isolation film(125) is formed inside the semiconductor film, and fills an isolation trench for defining a first semiconductor pattern(105) and a second semiconductor pattern(108). A first driving transistor(132) is formed in the first semiconductor pattern. A second transistor(134) is formed in the second semiconductor pattern. A floor surface of the isolation trench is a part of a top surface of the insulation film. At least one of the first driving transistor and the second driving transistor controls a high voltage higher than a power voltage.
Abstract translation: 目的：提供一种包括驱动晶体管的半导体器件，通过在绝缘膜上布置形成有驱动晶体管的半导体图案来减小半导体图案与相邻的半导体图案之间的间隔距离。 构成：在基板上依次配置绝缘膜和半导体膜。 在半导体膜内形成隔离膜（125），并填充用于限定第一半导体图案（105）和第二半导体图案（108）的隔离沟槽。 第一驱动晶体管（132）形成在第一半导体图案中。 第二晶体管（134）形成在第二半导体图案中。 隔离沟槽的地板表面是绝缘膜的上表面的一部分。 第一驱动晶体管和第二驱动晶体管中的至少一个控制高于电源电压的高电压。
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公开(公告)号：KR1020090106869A
公开(公告)日：2009-10-12
申请号：KR1020080032261
申请日：2008-04-07
Applicant: 삼성전자주식회사
CPC classification number: G11C16/3418 , G11C16/3427 , H01L27/11551
Abstract: PURPOSE: A three dimensional memory device and a driving method thereof are provided to reduce program disturbance by applying different well voltages to the wells of each layer in a program operation. CONSTITUTION: A three dimensional memory device(100) has a plurality of layers. One of the layers is selected. Wells(101,102) of the selected layer is biased to the first well voltage. A word line voltage is applied to the selected word line of the selected layer. The wells of the non-selected layers are biased to a second well voltage. The second well voltage is larger than the first well voltage. Each layer of the three dimensional memory device shares the word line.
Abstract translation: 目的：提供一种三维存储器件及其驱动方法，以通过在程序操作中向每层的阱施加不同的阱电压来减少编程干扰。 构成：三维存储装置（100）具有多个层。 选择其中一个图层。 所选择的层的阱（101,102）被偏置到第一阱电压。 字线电压被施加到所选层的所选字线。 未选择的层的阱被偏压到第二阱电压。 第二阱电压大于第一阱电压。 三维存储设备的每一层共享字线。
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公开(公告)号：KR1020090061334A
公开(公告)日：2009-06-16
申请号：KR1020070128313
申请日：2007-12-11
Applicant: 삼성전자주식회사
IPC: G05F3/24
CPC classification number: G05F1/613
Abstract: A shunt regulator and a semiconductor device equipped with the same are provided, which obtain the safe current shunt using the small occupied area. A control circuit(110) is combined with the gap between the first node and ground voltage. The control circuit generates the gate control signal in response to voltage and reference voltage of the first node. The bypass circuit(120) forms the first current path between ground voltage and the first node in response to the gate control signal. The protection circuit(130) has the MOS transistor completely turned on in response to the current flowing in the bypass circuit. The protection circuit forms the second current path between the first node and gap ground voltage.
Abstract translation: 提供了一种分流调节器和配备有它们的半导体器件，其使用小占用面积获得安全电流分流。 控制电路（110）与第一节点和地电压之间的间隙组合。 控制电路根据第一节点的电压和参考电压产生栅极控制信号。 旁路电路（120）响应于栅极控制信号形成接地电压和第一节点之间的第一电流路径。 保护电路（130）响应于在旁路电路中流动的电流而使MOS晶体管完全导通。 保护电路在第一节点和间隙接地电压之间形成第二电流路径。
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Patent Agency Ranking
公开(公告)号：KR1020090038309A
公开(公告)日：2009-04-20
申请号：KR1020070103735
申请日：2007-10-15
Applicant: 삼성전자주식회사
CPC classification number: H01M10/052 , H01M4/0404 , H01M4/0414 , H01M4/1391 , H01M4/1393
Abstract: An electrode for a secondary battery is provided to improve the capacity of electrode and cycle of a battery by improving the uniformity of an active material layer through the printing of low point ink. An electrode for a secondary battery comprises a current collector(10) and an active material layer formed by printing and drying ink(11) having the viscosity of 500 mPa . s on the current collector. The surface roughness Ra the current collector is 0.025-1.0 micron. The thickness the active material layer is 0.1-10 micron. The current collector is surface-treated with UV or the plasma.
Abstract translation: 提供一种用于二次电池的电极，用于通过印刷低点油墨来提高活性物质层的均匀性，从而提高电极的电容量和电池循环。 用于二次电池的电极包括集流器（10）和通过印刷和干燥具有500mPa的粘度的油墨（11）形成的活性物质层。 在当前收藏家。 集电体的表面粗糙度Ra为0.025〜1.0微米。 活性物质层的厚度为0.1-10微米。 集电器用UV或等离子体进行表面处理。
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公开(公告)号：KR1020080065119A
公开(公告)日：2008-07-11
申请号：KR1020070002110
申请日：2007-01-08
Applicant: 삼성전자주식회사
CPC classification number: H01L21/76237 , H01L21/765 , H01L21/823481 , H01L23/552 , H01L23/585 , H01L24/02 , H01L2223/6688 , H01L2924/12044
Abstract: A semiconductor device is provided to absorb the noise generated in a digital circuit region by forming an isolation layer and a conductive region on a boundary between a digital circuit region and an analog circuit region and by applying a ground voltage to the conductive region. A semiconductor substrate is prepared which includes a digital circuit region and an analog circuit region. An isolation layer(120) is formed on a boundary between the digital circuit region and an analog circuit region. A conductive region adjoins the lateral and bottom surfaces of the isolation layer. A ground pad(135) to which a ground voltage is applied is electrically connected to the conductive region. The conductive region can include an impurity region formed in the semiconductor substrate adjacent to the isolation layer.
Abstract translation: 提供一种半导体器件，用于通过在数字电路区域和模拟电路区域之间的边界上形成隔离层和导电区域并且通过向导电区域施加接地电压来吸收在数字电路区域中产生的噪声。 准备了包括数字电路区域和模拟电路区域的半导体衬底。 在数字电路区域和模拟电路区域之间的边界上形成隔离层（120）。 导电区域邻接隔离层的侧表面和底表面。 施加了接地电压的接地焊盘（135）电连接到导电区域。 导电区域可以包括形成在与隔离层相邻的半导体衬底中的杂质区域。
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公开(公告)号：KR100543455B1
公开(公告)日：2006-01-23
申请号：KR1020030034896
申请日：2003-05-30
Applicant: 삼성전자주식회사
IPC: H01L21/76
CPC classification number: H01L21/76224
Abstract: 본 발명은 공동이 없는 소자분리막을 형성하기 위한 반도체 소자의 소자분리막 형성방법에 관한 것으로, 반도체 기판을 제공하는 단계; 상기 반도체 기판 상에 패드 산화막과 패드 질화막을 순차로 형성하는 단계; 상기 반도체 기판에 트렌치를 형성하는 단계; 상기 트렌치를 매립하도록 상기 반도체 기판 상에 제1절연막을 형성하는 단계; 상기 제1절연막을 평탄화하는 단계; 상기 패드 산화막이 손상받지 않도록 상기 제1절연막을 일부 제거하는 단계; 상기 반도체 기판 상에 제2절연막을 형성하는 단계; 상기 제2절연막을 평탄화하는 단계; 및 상기 패드 질화막을 제거하는 단계를 포함하는 것을 특징으로 한다. 이에 의하면, 소자분리막 내의 공동이 없는 소자분리막을 형성할 수 있게 되어 반도체 소자의 수율이 향상되고 신뢰성이 향상되는 효과가 있다. 또한, 패드 산화막을 식각 손상으로부터 보호할 수 있게 되어 이를 그대로 사용할 수 있는 효과도 있게 된다.
Abstract translation: 本发明涉及一种器件隔离方法用于形成无空腔形成器件隔离膜，所述方法包括的半导体器件：提供半导体衬底; 在半导体衬底上顺序地形成衬垫氧化物膜和衬垫氮化物膜; 在半导体衬底中形成沟槽; 在半导体衬底上形成第一绝缘膜以填充沟槽; 平面化第一绝缘膜; 去除第一绝缘膜的一部分，使得衬垫氧化膜不被损坏; 在半导体衬底上形成第二绝缘膜; 平面化第二绝缘膜; 并去除垫氮化物膜。 据此，可以在器件隔离膜中形成没有空腔的器件隔离膜，从而提高半导体器件的产量并提高可靠性。 另外，可以保护衬垫氧化膜免受蚀刻损伤，从而可以照原样使用。
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公开(公告)号：KR1020040037545A
公开(公告)日：2004-05-07
申请号：KR1020020066087
申请日：2002-10-29
Applicant: 삼성전자주식회사
IPC: H01L21/336
CPC classification number: H01L29/6656 , H01L21/76895 , H01L21/76897 , H01L27/11 , H01L29/6659
Abstract: PURPOSE: A method for forming a semiconductor device is provided to restrain voids from being generated at a gap between gate patterns and minimize the deterioration of leakage current characteristics due to an exposed low concentration impurity diffusion layer by using an etch stop layer. CONSTITUTION: A gate pattern(105) including a gate electrode(103) is formed on a semiconductor substrate(101). A low concentration impurity diffusion layer(107a) is formed at both sides of the gate pattern in the semiconductor substrate. A spacer is formed at both sidewalls of the gate pattern. A high concentration impurity diffusion layer(107b) is formed in the semiconductor substrate by implanting doped ions into the resultant structure using the gate pattern and spacer as a mask. Then, the spacer is removed from the resultant structure. A conformal etch stop layer(111) is formed on the entire surface of the resultant structure. The thickness of the etch stop layer has the same size as the width of the lower surface of the spacer.
Abstract translation: 目的：提供一种用于形成半导体器件的方法，以限制在栅极图案之间的间隙处产生空隙，并且通过使用蚀刻停止层使由于暴露的低浓度杂质扩散层引起的漏电流特性的劣化最小化。 构成：在半导体衬底（101）上形成包括栅电极（103）的栅极图案（105）。 在半导体衬底中的栅极图案的两侧形成低浓度杂质扩散层（107a）。 在栅极图案的两个侧壁处形成间隔物。 通过使用栅极图案和间隔物作为掩模将掺杂离子注入到所得结构中，在半导体衬底中形成高浓度杂质扩散层（107b）。 然后，从所得到的结构中除去间隔物。 在所得结构的整个表面上形成保形蚀刻停止层（111）。 蚀刻停止层的厚度与间隔物的下表面的宽度具有相同的尺寸。
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公开(公告)号：KR100299138B1
公开(公告)日：2001-11-02
申请号：KR1019990041545
申请日：1999-09-28
Applicant: 삼성전자주식회사
IPC: H04L12/28
Abstract: 본발명에따른에이티엠장치에서비실시간트래픽제어장치가, 수신되는셀들을저장하며피포(fifo)방식에의해출력하는수신버퍼와, 상기수신버퍼의출력셀들을헤더정보에의해라우팅하는스위치와, 상기스위치의출력셀들을저장하며피포방식에의해송신하는송신버퍼와, 상기송신버퍼의양을감시하여임계치에이르면상기수신버퍼로경고신호를출력하고, 설정치이하가되면상기경고신호를해제하도록통보하여전송데이타의양을조정하는출력큐감시부로구성된것을특징으로한다.
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