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公开(公告)号：KR101194840B1
公开(公告)日：2012-10-25
申请号：KR1020060136821
申请日：2006-12-28
Applicant: 삼성전자주식회사
CPC classification number: G11C11/5628 , G11C16/10 , G11C2211/5642
Abstract: 3개의 래치를 이용하는 메모리 셀 프로그래밍 방법 및 반도체 메모리 장치가 개시된다. 본 발명에 따른 메모리 셀 프로그래밍 방법은, 제1래치에 저장된 데이터의 k-1(k는 2이상의 자연수)번째 비트를 제3래치에 저장하는 단계, 데이터의 k번째 비트를 제1래치에 저장하는 단계, 제1래치에 저장된 k번째 비트를 제2래치에 저장하는 단계, 및 제3래치에 저장된 k-1번째 비트를 참조하여 제2래치에 저장된 k번째 비트를 메모리 셀에 기입하는 단계를 구비한다.
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公开(公告)号：KR101169396B1
公开(公告)日：2012-07-30
申请号：KR1020060133093
申请日：2006-12-22
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/115 , B82Y10/00 , G11C16/0483 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L27/1203
Abstract: 고집적 비휘발성 메모리 소자 및 그 동작 방법이 제공된다. 비휘발성 메모리 소자는 반도체층을 포함한다. 복수의 상부 제어 게이트 전극들은 상기 반도체층 상에 배열된다. 복수의 하부 제어 게이트 전극들은 상기 반도체층의 아래에 배열되고, 상기 복수의 상부 제어 게이트 전극들과 엇갈리게 배치된다. 복수의 상부 전하 저장층들은 상기 반도체층 및 상기 상부 제어 게이트 전극들 사이에 각각 개재된다. 그리고, 복수의 하부 전하 저장층들은 상기 반도체층 및 상기 하부 제어 게이트 전극들 사이에 각각 개재된다.
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公开(公告)号：KR101108709B1
公开(公告)日：2012-01-30
申请号：KR1020070069978
申请日：2007-07-12
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/20
CPC classification number: H01L29/045 , H01L21/823412 , H01L24/32 , H01L24/83 , H01L27/11521 , H01L27/11568 , H01L29/7781 , H01L29/7842 , H01L29/7849 , H01L29/792 , H01L2224/2919 , H01L2224/838 , H01L2924/01013 , H01L2924/01019 , H01L2924/01032 , H01L2924/01033 , H01L2924/0104 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/0665 , H01L2924/00
Abstract: 개시된 반도체 장치는 제1 기판, 복수의 셀 트랜지스터들 및 제2 기판을 포함한다. 제1 기판은 제1 면과 제1 면과 대향하는 제2 면을 갖는다. 셀 트랜지스터들은 제1 기판 제1 면에 형성되고, 일 방향으로 연장되도록 배열된다. 제2 기판은 제1 기판의 제2 면과 면접하여 제1 기판을 지지하고, 제1 기판과 면접하는 그 상부면이 휘어진 곡선을 형상을 가지며, 상부면과 면접하는 제1 기판에 셀 트랜지스터들이 연장된 방향으로 인장 응력을 가한다. 따라서, 제1 기판에 인장 응력을 가하여 셀 트랜지스터들의 채널 영역 내에서 캐리어의 이동성을 향상시킬 수 있다.
Abstract translation: 所公开的半导体器件包括第一衬底，多个单元晶体管和第二衬底。 第一基板具有第一表面和与第一表面相对的第二表面。 单元晶体管形成在第一衬底第一表面上并且被布置成沿一个方向延伸。 的第二基板是具有一所涉及的反射弯曲的顶部表面的形状，在上表面上的单元晶体管和采访第一基底用于通过与所述第一基板的所述第二侧的采访支承的第一基板，和采访到第一基底 在延伸方向施加拉应力。 因此，拉伸应力可以施加到第一衬底以改善单元晶体管的沟道区内的载流子迁移率。
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公开(公告)号：KR1020090003909A
公开(公告)日：2009-01-12
申请号：KR1020070067672
申请日：2007-07-05
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L21/28273 , H01L21/02252 , H01L27/11521
Abstract: The non-volatile memory device and manufacturing method thereof are provided to increase the electron mobility in the channel region and to reduce the saturation drain current by forming first and second element isolation regions as different insulating materials. The semiconductor substrate(10) comprises the active area(11) extended to the first direction. The first element isolation region(20) is adjacent to the active area of the semiconductor substrate to the first direction. The first element isolation regions have the first stress. The second element isolation region(30) is adjacent to both end parts of the active area. The second element isolation regions have the second stress smaller than the first stress.
Abstract translation: 提供非易失性存储器件及其制造方法以增加通道区域中的电子迁移率，并通过将第一和第二元件隔离区域形成为不同的绝缘材料来降低饱和漏极电流。 半导体衬底（10）包括延伸到第一方向的有源区（11）。 第一元件隔离区域（20）与第一方向的半导体衬底的有源区域相邻。 第一元件隔离区域具有第一应力。 第二元件隔离区域（30）与有源区域的两端部相邻。 第二元件隔离区域具有小于第一应力的第二应力。
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公开(公告)号：KR1020080104958A
公开(公告)日：2008-12-03
申请号：KR1020080038175
申请日：2008-04-24
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L27/11521 , H01L21/28273 , H01L21/3213 , H01L29/513 , H01L29/517
Abstract: A non-volatile memory device and the manufacturing method thereof are provided to improve the thickness property of dielectric layer pattern including the high dielectric material. A non-volatile memory device comprises the semiconductor substrate(100), the tunnel oxide layer pattern(102a), and the gate structure(117). The tunnel oxide layer pattern is formed on the semiconductor substrate and is extended to the first direction. The gate structure comprises the floating gate(104b), the first conductive layer pattern(106b), the dielectric layer pattern(114a), the control gate(116a). The floating gate is formed on the tunnel oxide layer patterns in order to be arranged along the second direction. The first conductive layer pattern is formed on the floating gates in order to be arranged along the second direction. The dielectric layer pattern is formed in order to be extended to the second direction on first conductive layer patterns. The control gate is formed in order to be extended to the second direction on the dielectric layer pattern.
Abstract translation: 提供了一种非易失性存储器件及其制造方法，以改善包括高电介质材料的介电层图案的厚度特性。 非易失性存储器件包括半导体衬底（100），隧道氧化物层图案（102a）和栅极结构（117）。 隧道氧化物层图案形成在半导体衬底上并延伸到第一方向。 栅极结构包括浮置栅极（104b），第一导电层图案（106b），介电层图案（114a），控制栅极（116a）。 浮动栅极形成在隧道氧化物层图案上，以沿着第二方向排列。 第一导电层图案形成在浮动栅极上，以沿第二方向布置。 为了在第一导电层图案上向第二方向延伸形成电介质层图案。 控制栅极形成为在电介质层图案上延伸到第二方向。
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Patent Agency Ranking
公开(公告)号：KR1020080097853A
公开(公告)日：2008-11-06
申请号：KR1020070043216
申请日：2007-05-03
Applicant: 삼성전자주식회사
IPC: H01L21/28 , H01L21/3205 , H01L27/115 , H01L21/8247
CPC classification number: H01L27/105 , H01L23/5222 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11531 , H01L27/11568 , H01L2924/0002 , H01L21/28273 , H01L2924/00
Abstract: A conductive structure and a method of formation thereof are provided to reduce the parasitic capacitance between the conductive layer patterns. The conductive construct includes the first interlayer insulating(102) film formed on the substrate(100); first layer conductive layer patterns(110) equipped on the first interlayer insulating film; the insulating film structure(115) having the recess among first layer conductive layer patterns; the second level conductive layer pattern(118) in which the lower surface is positioned higher than the lower surface of the first layer conductive layer pattern. The second level conductive layer pattern is positioned in the recess which is included in the insulating film structure.
Abstract translation: 提供导电结构及其形成方法以减小导电层图案之间的寄生电容。 导电构造包括形成在基板（100）上的第一层间绝缘膜（102）; 配置在第一层间绝缘膜上的第一层导电层图案（110） 所述绝缘膜结构（115）在所述第一层导电层图案中具有所述凹部; 第二级导电层图案（118），其中下表面位于比第一层导电层图案的下表面高的位置。 第二级导电层图案位于包括在绝缘膜结构中的凹槽中。
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公开(公告)号：KR1020080024583A
公开(公告)日：2008-03-19
申请号：KR1020060088851
申请日：2006-09-14
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L27/11521 , H01L21/31144 , H01L21/76838 , H01L27/11568
Abstract: A method for manufacturing a nonvolatile memory device and a structure thereof are provided to reduce a contact area of a tunnel oxide layer and a semiconductor substrate by etching the semiconductor substrate on which a gate pattern is formed to fabricate a trench between adjacent gate patterns. A laminated material layer is formed on an upper portion of a semiconductor substrate(100). The laminated material is etched to form a gate pattern. An isotropic etching process is performed on the semiconductor substrate by using the gate pattern as a self-aligned etching mask. An anisotropic etching process is performed on the semiconductor substrate of which the isotropic etching process is completed by using the gate pattern as a self-aligned etching mask to form a trench between adjacent gate patterns. The laminated material layer is a layer on which a silicon oxide layer(102), a first polysilicon layer(104), an ONO(Oxide-Nitride-Oxide) layer(106) and on second polysilicon layer are sequentially laminated on an upper portion of the semiconductor substrate.
Abstract translation: 提供了一种用于制造非易失性存储器件及其结构的方法，通过蚀刻形成有栅极图案的半导体衬底来减小隧道氧化物层和半导体衬底的接触面积，以在相邻栅极图案之间制造沟槽。 层叠材料层形成在半导体衬底（100）的上部。 蚀刻层压材料以形成栅极图案。 通过使用栅极图案作为自对准蚀刻掩模，在半导体衬底上进行各向同性蚀刻处理。 通过使用栅极图案作为自对准蚀刻掩模在其各向同性蚀刻工艺完成的半导体衬底上进行各向异性蚀刻工艺，以在相邻栅极图案之间形成沟槽。 层叠材料层是在上部依次层叠有氧化硅层（102），第一多晶硅层（104），ONO（氧化物 - 氮化物 - 氧化物）层（106）和第二多晶硅层上的层 的半导体衬底。
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公开(公告)号：KR1020040058560A
公开(公告)日：2004-07-05
申请号：KR1020020084866
申请日：2002-12-27
Applicant: 삼성전자주식회사
IPC: H01L27/115
Abstract: PURPOSE: A flash memory device and a forming method thereof are provided to increase the coupling ratio between a floating gate and a control gate by controlling the depth of a contact hole. CONSTITUTION: A flash memory device includes a plurality of word lines(85). The word line includes a lower floating gate(87) and an upper floating gate(93) on the lower floating gate in a contact hole. The contact hole is formed through an interlayer dielectric(89). The upper floating gate is formed like a sidewall spacer. The word line further includes a control gate(97) for completely filling the contact hole and a dielectric layer(95) on the lower and upper floating gate for isolating the control gate from the lower and upper floating gate.
Abstract translation: 目的：提供闪速存储器件及其形成方法，以通过控制接触孔的深度来增加浮动栅极和控制栅极之间的耦合比。 构成：闪存器件包括多个字线（85）。 字线包括在接触孔中的下浮动栅极上的下浮动栅极（87）和上浮置栅极（93）。 接触孔通过层间电介质（89）形成。 上部浮动栅极形成为侧壁间隔物。 字线还包括用于完全填充接触孔的控制栅极（97）和用于将控制栅极与下部和上部浮动栅极隔离的下部和上部浮动栅极上的介电层（95）。
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公开(公告)号：KR1020020032760A
公开(公告)日：2002-05-04
申请号：KR1020000063396
申请日：2000-10-27
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L27/11526 , H01L27/105 , H01L27/11529 , H01L27/11531 , H01L29/42324 , H01L29/511
Abstract: PURPOSE: A non-volatile memory device and a fabrication method thereof are provided to prevent etch damage applied to a semiconductor substrate in a peripheral region while a word line pattern and a gate pattern are formed. CONSTITUTION: After first and second active areas are defined respectively in a cell array region(a) and the peripheral region(b) of the semiconductor substrate(51), the word line pattern(74a) running across the first active area and the gate pattern(74b) running across the second active area are formed. The word line pattern(74a) has a control gate electrode(69c), a floating gate(57f) interposed between the first active area and the control gate electrode(69c), and the first gate interlayer dielectric layer(64a) between the floating gate(57f) and the control gate electrode(69c). The gate pattern(74b) has a gate electrode(57g), a dummy gate electrode(69d) partly covering the gate electrode(57g), and the second gate interlayer dielectric layer(64b) interposed between the gate electrode(57g) and the dummy gate electrode(69d). Particularly, the second gate interlayer dielectric layer(64b) is thicker than the first gate interlayer dielectric layer(64a), so that the second active area in the peripheral region(b) is preserved from etch damage.
Abstract translation: 目的：提供一种非易失性存储器件及其制造方法，以防止在形成字线图形和栅极图案的同时在外围区域中施加到半导体衬底上的蚀刻损伤。 构成：在半导体衬底（51）的单元阵列区域（a）和周边区域（b）分别定义第一和第二有源区域之后，跨越第一有源区域和栅极的字线图案（74a） 形成贯穿第二有源区域的图案（74b）。 字线图案（74a）具有控制栅电极（69c），插入在第一有源区和控制栅电极（69c）之间的浮置栅极（57f），浮置栅极 栅极（57f）和控制栅电极（69c）。 栅极图案（74b）具有栅电极（57g），部分覆盖栅极电极（57g）的虚设栅电极（69d）和介于栅极电极（57g）和栅极电极 虚拟栅电极（69d）。 特别地，第二栅极层间介质层（64b）比第一栅极层间介质层（64a）厚，使得外围区域（b）中的第二有源区域被保护而不受蚀刻损伤。
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公开(公告)号：KR1020020022940A
公开(公告)日：2002-03-28
申请号：KR1020000055509
申请日：2000-09-21
Applicant: 삼성전자주식회사
IPC: H01L21/76
CPC classification number: H01L27/11526 , H01L21/76229 , H01L21/823462 , H01L21/823481 , H01L27/105 , H01L27/11541 , Y10S438/981
Abstract: PURPOSE: A method for fabricating a trench-isolation semiconductor device is provided to improve isolation reliability, by performing an effective isolation process while an ion implantation layer for a channel stop is formed, without an additional process. CONSTITUTION: A gate insulation layer(220,221) has different thicknesses in a cell region and a high voltage region of a substrate(210). An etch passivation layer(240) is stacked on the gate insulation layer. An etch mask pattern exposing a trench region is formed. The etch passivation layer is etched by using the etch mask pattern, and a gate insulation layer is etched until the gate insulation layer in the cell region is completely eliminated. The gate insulation layer remaining in the high voltage region is removed to expose substrate silicon by using etchant of which the etch selectivity regarding the substrate and the gate insulation layer is from 1:1 to 3:1. An etch process regarding the exposed substrate in the high voltage region is performed for a predetermined interval of time to form an isolation trench.
Abstract translation: 目的：提供一种用于制造沟槽隔离半导体器件的方法，通过在没有额外的工艺形成用于沟道停止的离子注入层的同时执行有效的隔离工艺来提高隔离可靠性。 构成：栅极绝缘层（220,221）在衬底（210）的单元区域和高电压区域中具有不同的厚度。 蚀刻钝化层（240）堆叠在栅极绝缘层上。 形成暴露沟槽区域的蚀刻掩模图案。 通过使用蚀刻掩模图案蚀刻蚀刻钝化层，并且蚀刻栅极绝缘层，直到电池区域中的栅极绝缘层被完全消除。 通过使用腐蚀剂去除残留在高电压区域中的栅极绝缘层，以暴露衬底硅，其蚀刻选择性相对于衬底和栅极绝缘层为1：1至3：1。 执行关于高电压区域中暴露的衬底的蚀刻工艺预定的时间间隔以形成隔离沟槽。
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