公开(公告)号：KR1020040014837A

公开(公告)日：2004-02-18

申请号：KR1020020047583

申请日：2002-08-12

Applicant: 삼성전자주식회사

Inventor： 김종호 ,  노미정 ,  김태수 ,  민병호 ,  조기원

IPC: G06F17/14

Abstract: PURPOSE: A composite FFT(Fast Fast Transform) calculating device, a composite FFT calculating method, and a recording medium adapted thereto are provided to minimize an FFT calculation speed. CONSTITUTION: Input registers(202,204) load data to be used for a calculation from read buses. Coefficient registers(206,208) load a sine value and a cosine value to be used for a calculation from the read buses. An adder(214) and a subtracter(216) add or subtract values stored in the Input registers(202,204). Multipliers(218,220) multiply an output of the subtracter(216) by outputs of the coefficient registers(206,208). Four storage registers(224,226,228,230) executes a complex calculation. Multiplexers(210,212) support operations of the adder(214) and the subtracter(216). A multiplexer(232) controls an output. A controller(234) controls operations of the above elements.

Abstract translation: 目的：提供一种复合FFT（Fast Fast Transform，快速变换）计算装置，复合FFT计算方法以及与其适配的记录介质，以最小化FFT计算速度。 构成：输入寄存器（202,204）从读取总线加载要用于计算的数据。 系数寄存器（206,208）从读总线加载用于计算的正弦值和余弦值。 加法器（214）和减法器（216）加或减加存储在输入寄存器（202,204）中的值。 乘数（218,220）将减法器（216）的输出乘以系数寄存器（206,208）的输出。 四个存储寄存器（224,226,228,230）执行一个复杂的计算。 多路复用器（210,212）支持加法器（214）和减法器（216）的操作。 多路复用器（232）控制输出。 控制器（234）控制上述元件的操作。

公开(公告)号：KR100322534B1

公开(公告)日：2002-03-18

申请号：KR1019990022920

申请日：1999-06-18

Applicant: 삼성전자주식회사

Inventor： 노미정 ,  이정석

IPC: G11C11/407

CPC classification number: G06F12/0893 ,  G06F2212/3042

Abstract: 디램에스램복합반도체장치및 이를이용한데이터전송방법이제공된다. 본발명의디램에스램복합반도체장치는주 메모리로서디램을포함하고, 캐시메모리로서에스램을포함한다. 본발명에서의디램의독출동작및 에스램의기입동작이디램독출제어신호에의하여동시에제어된다. 그리고디램의기입동작및 에스램의독출동작이디램기입제어신호에의하여동시에제어된다. 본발명에디램및 에스램복합반도체장치에의하면, 디램기입명령과디램독출명령을연속적으로줄 수있다. 따라서디램과에스램의데이터교환속도가현저히개선된다. 그리고디램의독출동작이완료된후에에스램의기입동작이시작도며, 또한에스램의독출동작이완료된후에디램의기입동작이시작되므로무효한데이터로인한전류의소모가없다. 또한, 디램쪽의명령으로에스램을제어함으로그 제어가용이하게될 수있다.

公开(公告)号：KR100306468B1

公开(公告)日：2001-11-02

申请号：KR1019990040424

申请日：1999-09-20

Applicant: 삼성전자주식회사

Inventor： 노미정

IPC: G11C11/401

Abstract: 본발명은반도체메모리장치및 입출력라인프리차지방법에관한것으로서, 특히본 발명의장치는제 1 및제 2 메모리영역상에서, 각각컬럼방향으로확장되고로우방향으로반복적으로배치된복수의제 1 및제 2 지역입출력라인쌍들과, 각제 1 및제 2 지역입출력라인쌍들을각각프리차지하기위한복수의제 1 및제 2 프리차지수단들과, 제 1 및제 2 메모리영역들사이에배치되고, 각제 1 및제 2 지역입출력라인쌍들의종단에각각연결된복수의제 1 및제 2 스위칭수단들과, 제 1 및제 2 메모리영역들사이에배치되고, 대응하는제 1 및제 2 스위칭수단들의각 출력들이공통으로연결되고, 대응하는입출력센스증폭기에각각연결된복수의광역입출력라인쌍들과, 대기모드에서는복수의제 1 및제 2 스위칭수단들을모두턴온상태로제어하고, 제 1 메모리영역의리드또는라이트명령에응답하여복수의제 2 스위칭수단들을턴오프시키고, 리드또는라이트명령에뒤따르는명령에응답하여턴오프된복수의제 2 스위칭수단들을턴온시켜서복수의제 1 및제 2 프리차지수단들을통하여복수의제 1 및제 2 지역입출력라인쌍들및 복수의광역입출력라인쌍들이동시에프리차지되도록제어하는스위칭제어수단을포함한다. 따라서, 본발명에서는광역입출력라인쌍의프리차지수단을제거할수 있어서칩 사이즈및 전력소모를줄일수 있다.

公开(公告)号：KR100305608B1

公开(公告)日：2001-10-17

申请号：KR1019990055260

申请日：1999-12-06

Applicant: 삼성전자주식회사

Inventor： 곽진석 ,  송호영 ,  노미정 ,  조호열

IPC: G11C11/407

Abstract: 본발명은블록라이트기능을가진반도체메모리장치및 블록라이트방법에관한것으로서, 특히본 발명의장치는라이트제어신호에응답하여입력된데이터를각 입출력라인쌍들에구동하기위한복수의라이트드라이버들과, 입출력라인쌍과대응하는비트라인쌍의사이에각각연결되고, 블록라이트사이클중에는그룹단위로활성화되는복수의컬럼선택기들과, 대응하는비트라인쌍에각각연결되고, 비트라인쌍에인가되는데이터를센싱하여증폭하기위한복수의비트라인센스증폭기들과, 각비트라인에연결된복수의메모리셀들로각각구성된복수의메모리컬럼들과, 각입출력라인쌍에각각연결되고, 블록라이트사이클동안에라이트마스크신호에응답하여마스킹된입출력라인쌍에는부하전류를공급하고나머지마스킹되지않은입출력라인쌍에는부하전류를공급하지않는복수의부하전류소스들을포함한다. 따라서, 본발명에서는입출력라인쌍을알루미늄과같이면저항이작은금속재료를사용한반도체메모리장치에서메모리코아의변경없이블록라이트기능을실현할수 있다.

公开(公告)号：KR1020010054447A

公开(公告)日：2001-07-02

申请号：KR1019990055260

申请日：1999-12-06

Applicant: 삼성전자주식회사

Inventor： 곽진석 ,  송호영 ,  노미정 ,  조호열

IPC: G11C11/407

CPC classification number: G11C7/1096 ,  G11C5/063 ,  G11C7/06 ,  G11C7/1009 ,  G11C11/4091 ,  G11C11/4096

Abstract: PURPOSE: A semiconductor memory device having a block write function and a block write method are provided to prevent a data interference effect between activated columns by providing a load current to a pair of masked input/output line from an additional load current source during a block write cycle, and to perform the block write function without increasing an area of a memory core. CONSTITUTION: Input/output line pair(IO0,IOB0) is in a write masking state, and input/output line pair(IO7,IOB7) is in a block write state. Corresponding bit line pairs((BL0,BLB0),(BL1,BLB1),(BL7,BLB7)) are connected to the input/output line pair(IO0,IOB0) through column selectors(CS0-CS7). The column selectors comprises two NMOS transistors. In one NMOS transistor, a drain is connected to a bit line(BLi) and a source is connected to an input/output line(IOi) and a gate is connected to a column selection line(CSLi). In another NMOS transistor, a drain is connected to a bit line(BLBi) and a source is connected to an input/output line(IOBi) and a gate is connected to a column selection line(CSLi). The column selector is enabled one by one in a normal write cycle but in a block write mode eight column selectors are enabled simultaneously. Bit line sense amplifiers(SAMP0-SAMP7) to amplify data of a memory cell enabled by a word line are connected to each bit line pair. The bit line sense amplifier includes an NMOS amplifier(NSA) and a PMOS amplifier(PSA) arranged adjacent to the column selector. 256 memory cells are connected to each bit line pair to form a memory column. And, the first load current source(WLCSi) and the second load current source(RLCSi) and a write driver(WDi) are connected to each input/output line pair.

Abstract translation: 目的：提供具有块写入功能和块写入方法的半导体存储器件，以通过在一个块期间从额外的负载电流源向一对屏蔽的输入/输出线提供负载电流来防止激活的列之间的数据干扰效应 写周期，并且执行块写入功能而不增加存储器核心的面积。 构成：输入/输出线对（IO0，IOB0）处于写入屏蔽状态，输入/输出线对（IO7，IOB7）处于写入状态。 相应的位线对（（BL0，BLB0），（BL1，BLB1），（BL7，BLB7））通过列选择器（CS0-CS7）连接到输入/输出线对（IO0，IOB0）。 列选择器包括两个NMOS晶体管。 在一个NMOS晶体管中，漏极连接到位线（BLi），源极连接到输入/输出线（IOi），栅极连接到列选择线（CSLi）。 在另一个NMOS晶体管中，漏极连接到位线（BLBi），源极连接到输入/输出线（IOBi），栅极连接到列选择线（CSLi）。 列选择器在正常写周期中逐个启用，但在块写模式中，8个列选择器同时使能。 用于放大由字线使能的存储单元的数据的位线读出放大器（SAMP0-SAMP7）被连接到每个位线对。 位线读出放大器包括与列选择器相邻布置的NMOS放大器（NSA）和PMOS放大器（PSA）。 256个存储单元连接到每个位线对以形成存储器列。 并且，第一负载电流源（WLCSi）和第二负载电流源（RLCSi）以及写入驱动器（WDi）连接到每个输入/输出线对。

公开(公告)号：KR1020010002875A

公开(公告)日：2001-01-15

申请号：KR1019990022920

申请日：1999-06-18

Applicant: 삼성전자주식회사

Inventor： 노미정 ,  이정석

IPC: G11C11/407

CPC classification number: G06F12/0893 ,  G06F2212/3042

Abstract: PURPOSE: A DRAM SRAM compound semiconductor device is provided which transfers data effectively between a DRAM and a SRAM embodied on one chip. CONSTITUTION: The device includes a DRAM(100) as a main memory, and includes a SRAM(200) as a cache memory. A read operation of the DRAM and a write operation of the SRAM are controlled by a DRAM read control signal simultaneously, And a write operation of the DRAM and a read operation of the SRAM are controlled by a DRAM write control signal simultaneously. According to the DRAM and SRAM compound semiconductor device, a DRAM write command and a DRAM read command is given continuously. Therefore, the data exchange speed of the DRAM and the SRAM are improved steeply. And, after the read operation of the DRAM is completed, the write operation of the SRAM starts, and also because after the read operation of the SRAM is completed the write operation of the DRAM starts, there is no current consumption due to void data. Also, it is easy to control the SRAM because the SRAM is controlled by the command of the DRAM.

Abstract translation: 目的：提供一种DRAM SRAM化合物半导体器件，用于在一个芯片上体现DRAM和SRAM之间有效传输数据。 构成：该装置包括作为主存储器的DRAM（100），并且包括作为高速缓冲存储器的SRAM（200）。 DRAM的读取操作和SRAM的写入操作由DRAM读取控制信号同时控制，并且DRAM的写入操作和SRAM的读取操作同时由DRAM写入控制信号控制。 根据DRAM和SRAM化合物半导体器件，连续地给出DRAM写入命令和DRAM读取命令。 因此，DRAM和SRAM的数据交换速度急剧提高。 并且，在DRAM的读操作完成之后，SRAM的写操作开始，并且由于在SRAM的读操作完成之后，DRAM的写操作开始，所以不存在由于空数据导致的电流消耗。 此外，由于SRAM由DRAM的命令控制，因此易于控制SRAM。