公开(公告)号：KR1020090088651A

公开(公告)日：2009-08-20

申请号：KR1020080014063

申请日：2008-02-15

Applicant: 삼성전자주식회사

Inventor： 백승재 ,  최한메 ,  임주완 ,  김홍석 ,  이주열 ,  박광민 ,  최시영 ,  황기현

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L29/792 ,  H01L21/0223 ,  H01L21/02252 ,  H01L21/0226 ,  H01L29/4234 ,  H01L29/66833

Abstract: A nonvolatile memory device and a manufacturing method thereof are provided to improve reliability of a device by preventing concentration of an electron in interface between a charge trapping layer and a blocking layer during a programming or removing operation. A tunnel layer(110) is formed on a semiconductor substrate(100). A charge trapping layer(120) is formed on the tunnel layer. A first blocking layer(132) is formed on the charge trapping layer. A second blocking layer(134) is formed on the first blocking layer, and is made of material having a dielectric constant higher than the first blocking layer. A gate electrode is formed on the second blocking layer. A band gap of the first blocking layer is arranged in the gate electrode, and includes a source/drain region.

Abstract translation: 提供非易失性存储器件及其制造方法，以通过在编程或去除操作期间防止电荷在电荷捕获层和阻挡层之间的界面中的浓缩来提高器件的可靠性。 隧道层（110）形成在半导体衬底（100）上。 在隧道层上形成电荷捕获层（120）。 在电荷俘获层上形成第一阻挡层（132）。 第一阻挡层（134）形成在第一阻挡层上，并且由具有高于第一阻挡层的介电常数的材料制成。 在第二阻挡层上形成栅电极。 第一阻挡层的带隙设置在栅电极中，并且包括源/漏区。

公开(公告)号：KR1020090025597A

公开(公告)日：2009-03-11

申请号：KR1020070090567

申请日：2007-09-06

Applicant: 삼성전자주식회사

Inventor： 박광민 ,  백승재 ,  황기현 ,  최시영 ,  임주완 ,  김홍석

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: A flash memory device and a manufacturing method thereof are provided to reduce the loss of the electron in a horizontal direction by changing the property of a charge trapping layer by implanting the ion to the outside of the cell of a charge trap layer. A semiconductor substrate includes an active region(100) restricted by an element isolation layer(110). A tunnel insulating layer(120) is formed on a semiconductor substrate. A charge trap layer is formed on the semiconductor substrate. A blocking insulation layer(140) is formed on the charge trap layer. A control electrode(150) crosses the charge trap layer. An upper part(130b) of the element isolation layer of the charge trap layer has the hopping mobility lower than the upper part(130a) of an active region of the charge trap layer.

Abstract translation: 提供了一种闪速存储器件及其制造方法，通过将电离离子注入到电荷陷阱层的电池的外部，通过改变电荷俘获层的性质来减小电子在水平方向上的损耗。 半导体衬底包括由元件隔离层（110）限制的有源区（100）。 隧道绝缘层（120）形成在半导体衬底上。 在半导体衬底上形成电荷陷阱层。 在电荷陷阱层上形成阻挡绝缘层（140）。 控制电极（150）穿过电荷陷阱层。 电荷陷阱层的元件隔离层的上部（130b）的跳跃迁移率低于电荷陷阱层的有源区的上部（130a）。

公开(公告)号：KR1020090014658A

公开(公告)日：2009-02-11

申请号：KR1020070078750

申请日：2007-08-06

Applicant: 삼성전자주식회사

Inventor： 백성권 ,  박광민 ,  황기현 ,  노영진 ,  구본영

IPC: H01L27/115 ,  H01L21/8247 ,  H01L21/316

CPC classification number: H01L21/28273 ,  H01L21/0223 ,  H01L21/02247 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/66825

Abstract: A method of forming a layer and method of manufacturing a non-volatile memory device using the same is provided to improve the property of the semiconductor device by forming a film at interface which relatively the nitrogen distribution density is high. In a method of forming a layer and method of manufacturing a non-volatile memory device, an oxide film(102) for pad is formed on the substrate(100). A silicon-rich nitride layer(104) is formed on the oxide film for pad. The oxide film in which the nitrogen is accumulated is formed on the interface of the substrate by oxidizing the silicon-rich nitride layer. The silicon-rich nitride layer is formed after forming the silicon nitride film on the oxide film for pad by inserting silicon into the silicon nitride film.

Abstract translation: 提供一种形成层的方法和制造使用其的非易失性存储器件的方法，以通过在相对于氮分布密度高的界面处形成膜来改善半导体器件的性能。 在形成层的方法和制造非易失性存储器件的方法中，在衬底（100）上形成用于焊盘的氧化膜（102）。 在用于焊盘的氧化膜上形成富含硅的氮化物层（104）。 通过氧化富含硅的氮化物层，在衬底的界面上形成氮积存的氧化物膜。 通过将硅插入到氮化硅膜中，在用于焊盘的氧化物膜上形成氮化硅膜之后形成富硅氮化物层。

公开(公告)号：KR1020080010514A

公开(公告)日：2008-01-31

申请号：KR1020060070553

申请日：2006-07-27

Applicant: 삼성전자주식회사

Inventor： 노진태 ,  이성해 ,  황기현 ,  박광민 ,  이인선

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L29/66833 ,  H01L21/28282 ,  H01L29/42324

Abstract: A method of forming a dielectric layer structure and a method of forming a non-volatile memory device using the same are provided to improve the reliability of the non-volatile memory device and increase a programming and removal speed of the non-volatile memory device. A method of forming a dielectric layer structure includes the steps of: forming a first oxidization film(102) on a substrate(100); forming a preliminary silicon nitride film on the first oxidization film by using silicon source gas and nitrogen source gas as reaction gas; converting the preliminary silicon nitride film into a silicon nitride film(106) including excessive amount of silicon by flowing only the silicon source gas on the preliminary silicon nitride film by an in-situ method; and forming a second oxidization film(108) on the silicon nitride film. The method of forming the dielectric layer structure further includes a step of forming the silicon nitride film on multiple layers by repeating the steps of injecting the silicon source gas and the nitrogen source gas as the reaction gas, and flowing only the silicon source gas.

Abstract translation: 提供一种形成电介质层结构的方法和形成使用其的非易失性存储器件的方法，以提高非易失性存储器件的可靠性并增加非易失性存储器件的编程和移除速度。 形成电介质层结构的方法包括以下步骤：在衬底（100）上形成第一氧化膜（102）; 通过使用硅源气体和氮源气体作为反应气体，在第一氧化膜上形成预备的氮化硅膜; 通过原位法仅将硅源气体仅流过预置氮化硅膜，将初步氮化硅膜转换为包含过量硅的氮化硅膜（106）; 以及在所述氮化硅膜上形成第二氧化膜（108）。 形成电介质层结构的方法还包括通过重复注入硅源气体和氮源气体作为反应气体并仅流过硅源气体的步骤，在多层形成氮化硅膜的步骤。

公开(公告)号：KR1020070113676A

公开(公告)日：2007-11-29

申请号：KR1020060047231

申请日：2006-05-25

Applicant: 삼성전자주식회사

Inventor： 이성해 ,  이창현 ,  황기현 ,  백성권 ,  박광민

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L29/4234 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792

Abstract: An NVM(non-volatile memory) device is provided to decrease an electric field formed in a blocking insulation layer in a write/erase operation and improve a write/erase speed by using a high dielectric layer in the blocking insulation layer. A tunnel oxide layer(60) is formed on a semiconductor substrate(50). A charge trap layer(70) is formed on the tunnel insulation layer. A blocking insulation layer(110) is formed on the charge trap layer. A gate electrode(100) is formed on the blocking insulation layer. The blocking insulation layer has a stack structure of a high dielectric layer(90) and a barrier insulation layer(80) which has a higher energy barrier with respect to the charge trap layer than that with respect to the high dielectric layer. The barrier insulation layer has a thickness of 5~15 Å. The barrier insulation layer can be a silicon oxide layer. The charge trap layer may be a silicon nitride layer and the barrier insulation layer may be a silicon oxide layer which is formed by oxidizing an upper part of the silicon nitride layer.

Abstract translation: 提供NVM（非易失性存储器）器件以在写入/擦除操作中减少形成在阻挡绝缘层中的电场，并且通过在隔离绝缘层中使用高电介质层来提高写/擦除速度。 隧道氧化物层（60）形成在半导体衬底（50）上。 在隧道绝缘层上形成电荷陷阱层（70）。 在电荷陷阱层上形成阻挡绝缘层（110）。 栅极电极（100）形成在阻挡绝缘层上。 阻挡绝缘层具有高电介质层（90）和阻挡绝缘层（80）的叠层结构，其相对于电介质层具有比电介质层更高的能量势垒。 隔离层的厚度为5〜15。 阻挡绝缘层可以是氧化硅层。 电荷陷阱层可以是氮化硅层，并且阻挡层绝缘层可以是通过氧化氮化硅层的上部而形成的氧化硅层。