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公开(公告)号：KR1020110076135A
公开(公告)日：2011-07-06
申请号：KR1020090132764
申请日：2009-12-29
Applicant: 삼성전자주식회사
IPC: G11C7/02 , G11C7/00 , G11C7/10 , H03K19/0185
CPC classification number: G11C7/10 , G11C7/02 , G11C7/00 , H03K19/018528
Abstract: PURPOSE: A semiconductor memory device and a method of training the same are provided to improve the property of an output signal by offsetting a noise induced in a signal line adjacent to an output line. CONSTITUTION: In a semiconductor memory device and a method of training the same, Signal output units(211,212,213) output signal through a first signal line. A noise offset signal generator(230) generates a noise offset signal. The noise offset signal generator applies the noise offset signal to a second signal line. The noise offset signal offsets the noise induced in the second signal line. The first signal line and the second signal line are adjacent to each other. . Delay units(231,232,233) are connected to the first signal line and delay the signal.
Abstract translation: 目的：提供一种半导体存储器件及其训练方法，以通过抵消在与输出线相邻的信号线中感应出的噪声来改善输出信号的特性。 构成：在半导体存储器件及其训练方法中，信号输出单元（211,212,213）通过第一信号线输出信号。 噪声偏移信号发生器（230）产生噪声偏移信号。 噪声偏移信号发生器将噪声偏移信号施加到第二信号线。 噪声偏移信号抵消在第二信号线中感应的噪声。 第一信号线和第二信号线彼此相邻。 。 延迟单元（231,232,233）连接到第一个信号线并延迟信号。
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公开(公告)号：KR1020100117345A
公开(公告)日：2010-11-03
申请号：KR1020090036037
申请日：2009-04-24
Applicant: 삼성전자주식회사
CPC classification number: G11C7/22 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/4401 , G11C29/50012 , G11C2207/2254
Abstract: PURPOSE: A semiconductor memory device is provided to remove the time delay difference of data between a data training mode and a normal mode by including a variable delay unit to output a signal inputted at the data training mode and the normal mode corresponding to preset delay time. CONSTITUTION: A data training unit(110) outputs a write data driving signal by inputting a data signal. A variable delay unit(120) responds to a data training signal inputted from a memory controller(200) and outputs data signals by delaying a plurality of write data driving signals corresponding to the delay time. A data input and output unit(130) outputs a plurality of write data driving signals by inputting a plurality of data signals. The data input and output unit outputs a plurality of data signals by inputting lead data driving signals.
Abstract translation: 目的：提供一种半导体存储器件，用于通过包括可变延迟单元来输出在数据训练模式下输入的信号和对应于预设延迟时间的正常模式来消除数据训练模式和正常模式之间的数据的时间延迟差异 。 构成：数据训练单元（110）通过输入数据信号来输出写数据驱动信号。 可变延迟单元（120）响应从存储器控制器（200）输入的数据训练信号，并通过延迟对应于延迟时间的多个写入数据驱动信号来输出数据信号。 数据输入输出单元（130）通过输入多个数据信号来输出多个写入数据驱动信号。 数据输入和输出单元通过输入引导数据驱动信号输出多个数据信号。
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公开(公告)号：KR1020100111988A
公开(公告)日：2010-10-18
申请号：KR1020090030502
申请日：2009-04-08
Applicant: 삼성전자주식회사
CPC classification number: H03K5/1565 , H03K2005/0013 , G11C7/22
Abstract: PURPOSE: A semiconductor integrated circuit compensating a jitter and a jitter compensation method are provided to prevent a jitter effect by compensating the jitter due to noise. CONSTITUTION: A noise detecting circuit(210) detects the noise of a power source. A clock delaying circuit(220) receives a first clock. The clock delaying circuit delays the first clock. The clock delaying circuit outputs a second clock. A data transmission circuit(230) receives data and power source. The data transmission circuit is synchronized with the second clock to and output data.
Abstract translation: 目的：提供补偿抖动和抖动补偿方法的半导体集成电路，以通过补偿由噪声引起的抖动来防止抖动效应。 构成：噪声检测电路（210）检测电源的噪声。 时钟延迟电路（220）接收第一时钟。 时钟延迟电路延迟第一个时钟。 时钟延迟电路输出第二个时钟。 数据传输电路（230）接收数据和电源。 数据传输电路与第二个时钟同步并输出数据。
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公开(公告)号：KR1020100094859A
公开(公告)日：2010-08-27
申请号：KR1020090014041
申请日：2009-02-19
Applicant: 삼성전자주식회사
CPC classification number: H03L7/0896 , H02M3/07
Abstract: PURPOSE: An asymmetry charge pump and a phase locked loop including the same are provided to reduce a lock screw by including an asymmetry charge pump to control the time when the current is inputted to the loop filter and the current is outputted from the loop filter. CONSTITUTION: A current source(121,122) generates a current inputted from the outside or current outputted to the outside through an output node. A switching circuit is connected between an output node(N2) and a current source. The switching circuit switches according to the phase difference of a reference signal and the feedback signal. The switching circuit compares the charge charged to the outside and the charge discharged from the outside. A switching circuit(123) reduces a lock screw by controlling the time when the current is outputted or inputted according to the comparison result.
Abstract translation: 目的：提供一种不对称电荷泵和包括该非对称电荷泵的锁相环，通过包括不对称电荷泵来控制锁定螺丝，以控制电流输入到环路滤波器的时间，并从环路滤波器输出电流。 构成：电流源（121,122）通过输出节点产生从外部输入的电流或输出到外部的电流。 开关电路连接在输出节点（N2）和电流源之间。 开关电路根据参考信号和反馈信号的相位差进行切换。 开关电路将从外部充电的电荷和从外部释放的电荷进行比较。 切换电路（123）根据比较结果控制电流输出或输入的时间来减少锁定螺丝。
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公开(公告)号：KR1020090076187A
公开(公告)日：2009-07-13
申请号：KR1020080001985
申请日：2008-01-08
Applicant: 삼성전자주식회사
IPC: G11C11/407 , G11C11/4076
CPC classification number: H03L7/0812 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C2207/107 , H04L7/0008 , H04L7/0091
Abstract: A semiconductor device, an operation method of semiconductor device and a semiconductor system are provided to select the clocking structure according to the first and the second clock signals, the first clock signal and the jitter property of the phase locked loop. A semiconductor system comprises a controller(20) and a semiconductor device(30). The semiconductor device comprises a selecting circuit(31) and a phase detector(45). The selecting circuit outputs the first clock signal(WCK) of controller or the output signal of the phase locked loop(33) in response to the first selection signal(MRS1) of controller as the timing signal. The selecting circuit is the clocking circuit. The phase detector produces the voltage signal showing the phase difference between the timing signal of controller and the selecting circuit of the second clock signal(CK).
Abstract translation: 提供半导体器件，半导体器件的操作方法和半导体系统，以根据第一和第二时钟信号选择时钟结构，第一时钟信号和锁相环的抖动特性。 半导体系统包括控制器（20）和半导体器件（30）。 半导体器件包括选择电路（31）和相位检测器（45）。 响应于控制器的第一选择信号（MRS1）作为定时信号，选择电路输出控制器的第一时钟信号（WCK）或锁相环（33）的输出信号。 选择电路是时钟电路。 相位检测器产生表示控制器的定时信号和第二时钟信号（CK）的选择电路之间的相位差的电压信号。
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Patent Agency Ranking
公开(公告)号：KR100801055B1
公开(公告)日：2008-02-04
申请号：KR1020060100513
申请日：2006-10-16
Applicant: 삼성전자주식회사
Inventor： 배승준
IPC: H04L27/01
CPC classification number: G11C7/1078 , G11C7/1087 , G11C11/4093
Abstract: A data receiver and a semiconductor device having the same are provided to decrease a circuit size and current consumption of the data receiver and to increase an operation speed of the semiconductor device. A data receiver of a semiconductor device includes first to n-th equalizers(410-440). Each of the equalizers includes sense amplifiers(412,422) and latches(414,424). The sense amplifier amplifies a difference between input data and a first reference voltage or a difference between the input data and a second reference voltage, and outputs a sense amplifier output signal, in response to a corresponding clock signal and a control signal. The latch latches the sense amplifier output signal. The control signal for the first equalizer is the sense amplifier output signal from the n-th equalizer. The control signal of the i-th equalizer is the sense amplifier output signal from the (i-1)-th equalizer.
Abstract translation: 提供数据接收器和具有该数据接收器的半导体器件以减小数据接收器的电路尺寸和电流消耗，并提高半导体器件的操作速度。 半导体器件的数据接收器包括第一至第N均衡器（410-440）。 每个均衡器包括读出放大器（412,422）和锁存器（414,424）。 感测放大器放大输入数据和第一参考电压之间的差或输入数据与第二参考电压之间的差，并响应于相应的时钟信号和控制信号输出读出放大器输出信号。 锁存器锁存读出放大器输出信号。 用于第一均衡器的控制信号是来自第n均衡器的读出放大器输出信号。 第i个均衡器的控制信号是来自第（i-1）均衡器的读出放大器输出信号。
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公开(公告)号：KR1020070064930A
公开(公告)日：2007-06-22
申请号：KR1020050125551
申请日：2005-12-19
Applicant: 삼성전자주식회사
CPC classification number: G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C7/02
Abstract: A high speed interface semiconductor memory device and a method thereof are provided to reduce circuit area and power consumption by using a quadrature strobe signal. A clock signal generation circuit generates a first and a second clock signal having a phase difference of 90 degrees. A first group data transmission circuit(310) multiplexes and transmits first group data in response to the first and the second clock signal. A second group data transmission circuit(320) multiplexes second group data in response to the first and the second clock signal. A first strobe signal transmission circuit(330) transmits a first strobe signal based on the first clock signal. A second strobe signal transmission circuit(340) transmits a second strobe signal based on the second clock signal. At least one of the first and the second strobe signal transmission circuit controls the phase of a corresponding strobe signal, on the basis of data error information fed back from a receiver semiconductor device.
Abstract translation: 提供了一种高速接口半导体存储器件及其方法，通过使用正交选通信号来减少电路面积和功耗。 时钟信号产生电路产生具有90度相位差的第一和第二时钟信号。 第一组数据传输电路（310）响应于第一和第二时钟信号复用并发送第一组数据。 第二组数据传输电路（320）响应于第一和第二时钟信号复用第二组数据。 第一选通信号发送电路（330）基于第一时钟信号发送第一选通信号。 第二选通信号发送电路（340）基于第二时钟信号发送第二选通信号。 第一和第二选通信号传输电路中的至少一个基于从接收器半导体器件反馈的数据错误信息来控制对应的选通信号的相位。
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公开(公告)号：KR1020070049826A
公开(公告)日：2007-05-14
申请号：KR1020050107023
申请日：2005-11-09
Applicant: 삼성전자주식회사
Inventor： 배승준
IPC: H01L21/02
Abstract: 본 발명은 케이블 유동 방지 기능을 구비한 반도체 제조 장치에 관한 것으로,
이를 실현하기 위하여 본 발명은, 반도체 제조 공정을 수행하는 공정 챔버; 상기 공정 챔버 내의 온도를 측정하는 열전대; 상기 공정 챔버의 외측에 결합하여 상기 열전대를 상기 공정 챔버 내로 삽입하기 위한 홀을 형성하는 케이블 커넥터; 및 상기 열전대와 연결되어 있으며 상기 열전대로부터 전달되는 상기 온도에 따라 상기 공정 챔버 내의 온도를 조절하는 컨트롤러;를 포함하여 구성하는 반도체 제조 장치에 있어서, 상기 케이블 커넥터는 상기 열전대의 케이블의 미동을 방지하는 케이블 미동 방지부를 포함하고 있으며, 상기 케이블 미동 방지부는 실리콘러버와 케이블 보호 몸체의 사이에서 상기 케이블을 파지하는 원통형 모양의 케이블 파지부; 및 상기 케이블 파지부의 일측을 따라 "ㄷ" 모양으로 연장되어 상기 케이블 보호 몸체의 하단까지 형성하며 상기 케이블 보호 몸체의 하단 일측을 파지하는 걸림부;를 포함하여 구성하는 것을 특징으로 하는 케이블 유동 방지 기능을 구비한 반도체 제조 장치를 제공한다.
본 발명에 의하면 공정 챔버 내의 온도를 측정하는 열전대가 유동되는 것을 방지할 수 있으므로, 온도 측정 불량으로 인한 공정 에러 및 이로 인한 공정 진행 중의 웨이퍼 손실의 문제점을 해소할 수 있는 반도체 제조 장치를 제공할 수 있는 효과가 있다.
열전대(Thermo Couple), 히팅 챔버, 웨이퍼, 케이블(Cable)-
公开(公告)号：KR100674953B1
公开(公告)日：2007-01-26
申请号：KR1020050011016
申请日：2005-02-05
Applicant: 학교법인 포항공과대학교 , 삼성전자주식회사 , 포항공과대학교 산학협력단
IPC: G11C7/12
CPC classification number: H04L25/03038 , H04L7/0058
Abstract: 디지털 보정을 사용해 수신기의 오프셋 전압을 제거하고, 데이터와 클록 사이의 스큐를 제거하고, 등화 계수 설정을 통해 채널 간 간섭을 제거하는 등화 수신기가 개시된다. 본 발명에 따른 등화 수신기는 데이터를 전송하기 전에 초기 설정 모드에서 송신단에서 보낸 특정 데이터 패턴의 수신단 입력값을 샘플하여 현재와 이전의 데이터를 비교하여 등화 계수를 설정한다.
등화 수신기, DRAM, 인터페이스-
公开(公告)号：KR102237733B1
公开(公告)日：2021-04-08
申请号：KR1020140173680
申请日：2014-12-05
Applicant: 삼성전자주식회사
IPC: H03K19/0185
Abstract: 버퍼회로는제1 차동증폭기, 제2 차동증폭기, 제3 차동증폭기및 혼합기를포함한다. 제1 차동증폭기는입력신호및 기준전압신호에기초하여양성차동신호및 음성차동신호를생성한다. 제2 차동증폭기는양성차동신호및 음성차동신호에기초하여제1 신호를생성한다. 제3 차동증폭기는양성차동신호및 음성차동신호에기초하여제1 신호와위상이상이한제2 신호를생성한다. 혼합기는제1 신호와제2 신호를혼합한신호를출력신호로서출력한다.
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