公开(公告)号：KR100574927B1

公开(公告)日：2006-05-02

申请号：KR1019990047517

申请日：1999-10-29

Applicant: 삼성전자주식회사

Inventor： 정대현

IPC: H03D13/00

Abstract: 본 발명은 초기 락킹 시간을 줄여 고속동작이 가능하고 액티브 락킹시 지터성분을 줄일 수 있는 위상검출기에 관한 것으로, 이 위상검출기는 입력클럭과 출력클럭과의 위상차를 비교하여 위상차를 줄여 입력클럭과 출력클럭과의 위상을 일치시키기 위하여, 입력클럭과 출력클럭 사이의 앞서거나 뒤서는 위상차에 대하여 발생되는 제1 업(up) 신호 및 제1 다운(down) 신호 중 선택적으로 어느 하나만이 발생되는 제1 타입의 위상검출기와 이 위상차에 대하여 제2 업(up) 신호 및 제2 다운(down) 신호 둘다가 발생되는 제2 타입의 위상검출기와, 입력클럭, 제1 업/다운 신호 및 제2 업/다운 신호의 논리조합에 의하여 선택신호를 발생하는 선택제어부와, 선택신호에 응답하여 제1 및 제2 업 신호 중 어느 하나를 선택하고 제1 및 제2 다운 신호 중 어느 하나를 선택하는 먹스부를 구비한다. 그리하여, 먹스부에 의하여 선택되는 최종 업/다운 신호에 의하여 입력클럭과 출력클럭과의 위상을 일치시킨다.

公开(公告)号：KR1020060014936A

公开(公告)日：2006-02-16

申请号：KR1020040063707

申请日：2004-08-13

Applicant: 삼성전자주식회사

Inventor： 정대현

IPC: H04R3/12 ,  H04R5/04 ,  H04R1/10

CPC classification number: H04R5/04 ,  H04N5/2251 ,  H04R2420/05 ,  H04R3/12 ,  H04R1/1041 ,  H04R2420/03 ,  H04R2499/11

Abstract: Disclosed are an apparatus and method for selectively outputting an audio/video signal and a headphone signal through a common jack using an analog switch and a method thereof in a portable composite appliance. It is determined whether a specified plug is inserted into a common jack. If the specified plug that is identified as a headphone plug, a first logic level is output to a switching unit, which performs a switching operation and an audio signal is output to the headphones. Alternatively, if the inserted plug is identified as an audio/video plug, a second logic level is output to a switching unit, which performs a switching operation and an audio/video signal is output to the audio and video device.

公开(公告)号：KR1020030083870A

公开(公告)日：2003-11-01

申请号：KR1020020022260

申请日：2002-04-23

Applicant: 삼성전자주식회사

Inventor： 정대현

IPC: G11C11/4096

CPC classification number: G06F5/06 ,  G11C7/1072 ,  G11C7/222 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0045 ,  H04L7/02

Abstract: PURPOSE: A multi clock domain data input processing unit is provided which has a clock receiving synchronization circuit like a PLL(Phased Locked Loop) or a DLL(Delay Locked Loop), and a method for applying a clock signal according thereto is also provided. CONSTITUTION: According to the data input processing unit(200B), a clock receiving synchronization circuit generates an output clock signal by delaying a phase of the first clock signal. A data input part inputs applied data, in response to the first clock signal and the second clock signal applied with a different timing from the first clock signal for receiving clock conversion. And an input processing part(218) processes the data being output from the data input part using the output clock signal of the clock receiving synchronization circuit and the second clock signal.

Abstract translation: 目的：提供一种多时钟域数据输入处理单元，其具有类似于PLL（相位锁定环路）或DLL（延迟锁定环路）的时钟接收同步电路，并且还提供了根据该方法应用时钟信号的方法。 构成：根据数据输入处理单元（200B），时钟接收同步电路通过延迟第一时钟信号的相位来产生输出时钟信号。 数据输入部分响应于第一时钟信号和与从第一时钟信号不同的定时施加的第二时钟信号输入应用数据，以接收时钟转换。 并且输入处理部分（218）使用时钟接收同步电路的输出时钟信号和第二时钟信号来处理从数据输入部分输出的数据。

公开(公告)号：KR1020020090834A

公开(公告)日：2002-12-05

申请号：KR1020010054232

申请日：2001-09-04

Applicant: 삼성전자주식회사

Inventor： 김규현 ,  정대현

IPC: H03K5/13

CPC classification number: H03K5/08 ,  H03H11/265 ,  H03K5/13 ,  H03K2005/00071

Abstract: PURPOSE: A pulse signal transition delay control circuit is provided which can control a delay of a rising transition and a falling transition, and also can remove an unwanted delay due to a minimum capacitance by shorting a capacitor. CONSTITUTION: The integrated circuit comprises an input node(204) inputting an input signal(VIN) and a floating node(206) and a buffer(210) connected between the input node and the floating node. A detector(220) outputs an output voltage of the first level if a voltage of the floating node is below a threshold voltage, and otherwise, outputs an output voltage of the second level. The first reference port(230) transmits the first reference voltage(VR1), and the first capacitor(240) is connected between the floating node and the first reference port. And the first switch(250) is connected between the floating node and the first capacitor, and performs an opening/closing operation in response to the output voltage of the first and the second level.

Abstract translation: 目的：提供脉冲信号转换延迟控制电路，其可以控制上升转变和下降转变的延迟，并且还可以通过使电容器短路来消除由于最小电容引起的不期望的延迟。 构成：集成电路包括输入输入信号（VIN）和浮动节点（206）的输入节点（204）和连接在输入节点和浮动节点之间的缓冲器（210）。 如果浮动节点的电压低于阈值电压，则检测器（220）输出第一电平的输出电压，否则输出第二电平的输出电压。 第一参考端口（230）发送第一参考电压（VR1），并且第一电容器（240）连接在浮动节点和第一参考端口之间。 并且第一开关（250）连接在浮动节点和第一电容器之间，并且响应于第一和第二电平的输出电压执行打开/关闭操作。

公开(公告)号：KR1020020087294A

公开(公告)日：2002-11-22

申请号：KR1020010026418

申请日：2001-05-15

Applicant: 삼성전자주식회사

Inventor： 김규현 ,  정대현

IPC: G11C11/4093

CPC classification number: G11C7/1087 ,  G11C7/1078 ,  G11C2207/107

Abstract: PURPOSE: A synchronous DRAM(SDRAM) having a data latch circuit outputting data inputted by being synchronized to plural control signals is provided, which can reduce an effective data window and can minimize a chip area. CONSTITUTION: According to the synchronous DRAM(SDRAM), the first buffer(421) generates the first internal control signal(DQS_internal) by buffering an external control signal(DQS). The second buffer(431) generates the second internal control signal(DS) by buffering the external control signal, and the third buffer(441) generates an internal clock signal(PCLK) by buffering an external clock signal(CLK). And a data latch circuit(411) receives data from the external, and outputs the received data by being synchronized to the first and the second internal control signal and the internal clock signal in sequence.

Abstract translation: 目的：提供具有数据锁存电路的同步DRAM（SDRAM），其输出通过与多个控制信号同步输入的数据，这可以减少有效的数据窗口并且可以最小化芯片面积。 构成：根据同步DRAM（SDRAM），第一缓冲器（421）通过缓冲外部控制信号（DQS）产生第一内部控制信号（DQS_internal）。 第二缓冲器（431）通过缓冲外部控制信号产生第二内部控制信号（DS），第三缓冲器（441）通过缓冲外部时钟信号（CLK）产生内部时钟信号（PCLK）。 并且数据锁存电路（411）从外部接收数据，并且通过与第一和第二内部控制信号和内部时钟信号顺序同步来输出接收到的数据。

公开(公告)号：KR100335496B1

公开(公告)日：2002-05-08

申请号：KR1019990052999

申请日：1999-11-26

Applicant: 삼성전자주식회사

Inventor： 정대현 ,  이정배

IPC: G11C5/14

CPC classification number: G05F1/56 ,  G06F1/26 ,  G11C5/14 ,  G11C11/407 ,  G11C11/413 ,  H01L21/822 ,  H01L27/04

Abstract: 외부전원전압(VCC)이낮아지더라도안정적으로내부전원전압을발생하는내부전압발생회로가개시된다. 본발명은기준전압단자에연결되어기준전압을소정의전압레벨로낮추는제1 레벨시프터와, 내부전원전압단자에연결되어내부전원전압을소정의전압레벨로낮추는제2 레벨시프터와, 제1 및제2 레벨시프터의출력전압차를비교증폭하는차동증폭기와, 차동증폭기의출력에응답하여내부전원전압을발생하는드라이버를구비한다. 제1 및제2 레벨시프터는소스팔로우(source follower)로구현하고, 기준전압및 내부전원전압을문턱전압만큼강하시킨다. 따라서, 본발명의내부전압발생회로는 VCC 전압레벨이낮아지더라도안정적으로내부전원전압을발생시키고, 내부전원전압의전압레벨이떨어지더라도원래의기준전압과같은전압레벨로복구(restore)하며, 종래의내부전압발생회로에비하여소비전류가증가하지않는다.

公开(公告)号：KR1020010048334A

公开(公告)日：2001-06-15

申请号：KR1019990052999

申请日：1999-11-26

Applicant: 삼성전자주식회사

Inventor： 정대현 ,  이정배

IPC: G11C5/14

CPC classification number: G05F1/56 ,  G06F1/26 ,  G11C5/14 ,  G11C11/407 ,  G11C11/413 ,  H01L21/822 ,  H01L27/04

Abstract: PURPOSE: A circuit for generating internal voltage generating internal power voltage stably though external power voltage is low is provided to stably operate though an external power voltage is lowered. CONSTITUTION: The circuit includes the first and second level shifters, a differential amplifier(10) and a driver(20). The first level shifter is connected to a reference voltage terminal and lowers the reference voltage to a predetermined voltage level. The second level shifter is connected to an internal power voltage terminal and lowers an internal power voltage to a predetermined voltage level. The differential amplifier compares the difference of output voltages of the first and second level shifters and then amplifies. The driver generates the internal power voltage in response to an output of the differential amplifier. The first and second level shifters are embodied by source followers(30,40) and include transistors(MN3,MN4) and current sources(C1,C2). The reference voltage and the internal power voltage are connected to each gate of the transistors. The external power voltage is connected to each drain of the transistors. Each source of the transistors is connected as an input of the differential amplifier. The current sources are connected between each source of the transistors and ground voltage.

Abstract translation: 目的：通过外部电源电压低而稳定地产生内部电压产生内部电源电压的电路被提供以通过外部电源电压降低来稳定地工作。 构成：电路包括第一和第二电平移位器，差分放大器（10）和驱动器（20）。 第一电平移位器连接到参考电压端子并将参考电压降低到预定电压电平。 第二电平移位器连接到内部电源电压端子，并将内部电源电压降低到预定电压电平。 差分放大器比较第一和第二电平移位器的输出电压的差值，然后放大。 驱动器响应于差分放大器的输出产生内部电源电压。 第一和第二电平移位器由源极跟随器（30,40）实现，并且包括晶体管（MN3，MN4）和电流源（C1，C2）。 参考电压和内部电源电压连接到晶体管的每个栅极。 外部电源电压连接到晶体管的每个漏极。 晶体管的每个源作为差分放大器的输入端连接。 电流源连接在晶体管的每个源和接地电压之间。

公开(公告)号：KR1020010039217A

公开(公告)日：2001-05-15

申请号：KR1019990047517

申请日：1999-10-29

Applicant: 삼성전자주식회사

Inventor： 정대현

IPC: H03D13/00

Abstract: PURPOSE: A dual phase detector is provided to achieve the high speed operation of the dual phase detector by reducing the jitter component and saving the initial locking time of the dual phase detector. CONSTITUTION: The device includes the first type phase detector(71) which selectively generates the first up signal or the first down signal. The second type phase detector(72) generates both the second up signal and the second down signal. A selection control section(75) generates a selecting signal by logically combining an input clock, the first up and down signals and the first and second down signals. A pair of MUX sections(73,74) are provided to select one of the first and second up signals and one of the first and second down signals. The phase of the input clock is matched with the phase of the output clock by the final up and down signals selected by the mux sections(73,74).

Abstract translation: 目的：提供双相检测器，通过减少抖动分量并节省双相检测器的初始锁定时间，实现双相检测器的高速运行。 构成：该装置包括选择性地产生第一上升信号或第一下降信号的第一类型相位检测器（71）。 第二类型相位检测器（72）产生第二上升信号和第二下降信号。 选择控制部分（75）通过逻辑地组合输入时钟，第一上升和下降信号以及第一和第二下降信号来产生选择信号。 提供一对MUX部分（73,74）以选择第一和第二上升信号之一以及第一和第二下降信号之一。 输入时钟的相位与由多路复用器部分（73,74）选择的最终上下信号与输出时钟的相位相匹配。

公开(公告)号：KR1020120080052A

公开(公告)日：2012-07-16

申请号：KR1020110001493

申请日：2011-01-06

Applicant: 삼성전자주식회사

Inventor： 정대현

IPC: H04N5/232 ,  H04N5/225 ,  H04N5/77 ,  H04N5/907

CPC classification number: H04N5/23293 ,  H04N5/2251 ,  H04N5/772 ,  H04N5/907 ,  H04N5/23245

Abstract: PURPOSE: A photographing device and a photographing method thereof are provided to enable a user to use the photographing device without difficulty without respect to a right-handed person or a left-handed person. CONSTITUTION: If a sensing unit(130) senses rotation of a photographing device in a recording standby mode state, a control unit(140) changes a reading order of an image device. If the sensing unit senses rotation of the photographing device in a recording mode state, the control unit generates photographing data by a photographing unit(110) while maintaining the reading order.

Abstract translation: 目的：提供一种拍摄装置及其拍摄方法，以使用户能够毫无困难地使用拍摄装置，而不依赖于右撇子人或左撇子人。 构成：如果感测单元（130）在记录待机模式状态下感测拍摄装置的旋转，则控制单元（140）改变图像装置的读取顺序。 如果感测单元在记录模式状态下感测拍摄装置的旋转，则控制单元在保持读取顺序的同时由拍摄单元（110）生成拍摄数据。

公开(公告)号：KR1020090079084A

公开(公告)日：2009-07-21

申请号：KR1020080005043

申请日：2008-01-16

Applicant: 삼성전자주식회사

Inventor： 정대현 ,  박광일 ,  이재형 ,  김시홍 ,  배승준 ,  김진국

IPC: G11C7/10 ,  G11C8/18

CPC classification number: H03K19/0175 ,  H03F2203/45522

Abstract: A buffer and a semiconductor device including the same are provided to reduce signal distortion by operating within a wide frequency range stably. A differential amplifier(11) outputs a first differential signal and a second differential signal by amplifying the difference between the first input signal and the second input signal. A feedback inverter part(21) includes a first feedback inverter and a second feedback inverter. Each of the first and second feedback inverters includes a plurality of feedback resistors. The resistance of each feedback resistor is controlled in response to a flag signal. A coupling unit(13) includes a first capacitive element and a second capacitive element. The first capacitive element is connected between the first output terminal of the differential amplifier and the first inverter of the first output terminal. The second capacitive element is connected between the second output terminal of the differential amplifier and the input terminal of the second inverter.

Abstract translation: 提供缓冲器和包括该缓冲器的半导体器件以通过在宽频率范围内稳定地操作来减少信号失真。 差分放大器（11）通过放大第一输入信号和第二输入信号之间的差来输出第一差分信号和第二差分信号。 反馈逆变器部（21）包括第一反馈逆变器和第二反馈逆变器。 第一和第二反馈逆变器中的每一个包括多个反馈电阻器。 响应于标志信号来控制每个反馈电阻器的电阻。 耦合单元（13）包括第一电容元件和第二电容元件。 第一电容元件连接在差分放大器的第一输出端和第一输出端的第一反相器之间。 第二电容元件连接在差分放大器的第二输出端和第二反相器的输入端之间。