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公开(公告)号：KR1020040077272A
公开(公告)日：2004-09-04
申请号：KR1020030012772
申请日：2003-02-28
Applicant: 삼성전자주식회사
IPC: H01L21/311
CPC classification number: H01L29/6656 , H01L21/31116 , H01L21/76802 , H01L21/76829
Abstract: PURPOSE: A method for etching a silicon nitride layer is provided to reduce the etching speed of a silicon oxide layer and increase the etching speed of a silicon nitride layer by using the etching gas including CH2F2 gas under the substrate temperature of 40 and more degrees centigrade. CONSTITUTION: A buffer layer(22) is formed on an upper surface of a semiconductor substrate(10). The buffer layer is formed with a silicon oxide. A silicon nitride layer(24) is formed on an upper surface of the buffer layer. The silicon nitride layer is etched by using the etching gas including CH2F2 gas while the temperature of the semiconductor substrate exceeds 40 degrees centigrade. The etching gas further includes CF4 gas, inert gas such as argon, and O2 gas. The temperature of the semiconductor substrate is 60 to 100 degrees centigrade.
Abstract translation: 目的：提供一种蚀刻氮化硅层的方法，以降低硅氧化物层的蚀刻速度，并且在衬底温度为40摄氏度以上的条件下，通过使用包括CH 2 F 2气体的蚀刻气体来提高氮化硅层的蚀刻速度 。 构成：在半导体衬底（10）的上表面上形成缓冲层（22）。 缓冲层由氧化硅形成。 在缓冲层的上表面上形成氮化硅层（24）。 通过使用包括CH 2 F 2气体的蚀刻气体，同时半导体基板的温度超过40摄氏度来蚀刻氮化硅层。 蚀刻气体还包括CF 4气体，诸如氩气的惰性气体和O 2气体。 半导体基板的温度为60〜100摄氏度。
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公开(公告)号：KR1020040004911A
公开(公告)日：2004-01-16
申请号：KR1020020039138
申请日：2002-07-06
Applicant: 삼성전자주식회사
IPC: H01L21/3205
CPC classification number: H01L21/76897 , Y10S438/902 , Y10S438/976
Abstract: PURPOSE: A method for fabricating a self-aligned contact hole of a semiconductor device is provided to improve reliability and yield of the semiconductor device by minimizing a defect caused by a consumed nitride layer pattern for capping a conductive layer in a process for forming the self-aligned contact hole. CONSTITUTION: Conductive structures including a conductive layer pattern(103) and a passivation layer pattern formed on the upper surface and the sidewall of the conductive layer pattern are formed on a semiconductor substrate(100). The first insulation layer(114a) is formed to bury the gas between the conductive structures. The first insulation layer and the upper surface of the first insulation layer and the passivation layer pattern are sequentially etched back by a predetermined thickness so that the upper surface of the exposed passivation layer pattern is processed to be flat. The second insulation layer is formed on the resultant structure. A predetermined portion of the second and first insulation layers is selectively removed by a photolithography process to form a contact hole between the conductive structures wherein the semiconductor substrate is exposed to the contact hole.
Abstract translation: 目的：提供一种用于制造半导体器件的自对准接触孔的方法，以通过最小化在用于形成自身的工艺中用于封盖导电层的消耗的氮化物层图案所引起的缺陷来提高半导体器件的可靠性和产量 对准接触孔。 构成：在半导体衬底（100）上形成包括形成在导电层图案的上表面和侧壁上的导电层图案（103）和钝化层图案的导电结构。 第一绝缘层（114a）形成为在导电结构之间埋置气体。 将第一绝缘层和第一绝缘层的上表面和钝化层图案依次蚀刻回预定厚度，使得暴露的钝化层图案的上表面被处理成平坦的。 在所得结构上形成第二绝缘层。 通过光刻工艺选择性地去除第二和第一绝缘层的预定部分，以在半导体衬底暴露于接触孔的导电结构之间形成接触孔。
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Patent Agency Ranking
公开(公告)号：KR100380348B1
公开(公告)日：2003-04-11
申请号：KR1020010001572
申请日：2001-01-11
Applicant: 삼성전자주식회사
IPC: H01L21/3213
CPC classification number: H01L21/76897 , H01L21/823468 , H01L21/823475 , Y10S257/90
Abstract: A method for manufacturing a gate spacer for self-aligned contacts is provided. A gate stack is formed on a semiconductor substrate. A conformal dielectric layer is then formed over the gate stack. An etch-stop material layer, e.g., a photoresist layer, is formed over the conformal dielectric layer. Next, an upper portion of the etch stop material layer is removed to expose an upper portion of the conformal dielectric layer by techniques such as etching back. Subsequently, the exposed conformal dielectric layer is etched back using the remaining etch-stop material layer as an etch stopper. The remaining etch-stop material layer is removed and the etched-back conformal dielectric layer is again etched back to form a gate spacer.
Abstract translation: 提供了一种用于制造用于自对准触点的栅极隔离物的方法。 栅极叠层形成在半导体衬底上。 然后在栅极叠层上方形成共形介电层。 在共形电介质层上形成蚀刻停止材料层，例如光致抗蚀剂层。 接下来，通过诸如回蚀的技术去除蚀刻停止材料层的上部以暴露共形介电层的上部。 随后，使用剩余的蚀刻停止材料层作为蚀刻阻挡层来蚀刻暴露的保形介电层。 剩余的蚀刻停止材料层被去除并且再次回蚀刻保形的保形介电层以形成栅极间隔物。
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公开(公告)号：KR1020020060461A
公开(公告)日：2002-07-18
申请号：KR1020010001572
申请日：2001-01-11
Applicant: 삼성전자주식회사
IPC: H01L21/3213
CPC classification number: H01L21/76897 , H01L21/823468 , H01L21/823475 , Y10S257/90
Abstract: PURPOSE: A method for forming gate spacer of an SAC(Self-Aligned Contact) is provided to improve an open margin of the SAC and increase a size of a pad. CONSTITUTION: The conductive patterns(8,10) is formed on a semiconductor film(2) and an oxide film is formed on the conductive pattern. After forming an oxide film(12), the gate spacer(14) is deposited on the oxide and a semiconductor film. A photoresist is coated on the gate spacer and the photoresist and the oxide film is removed by etching at a fixed etching ratio. The residual photoresist is striped by ashing and the gate spacer is etched back. The photoresist is used as an etching barrier layer for etching the gate spacer. In case of etching the photoresist and the oxide film, the etching process uses a TCP(Transformer-Coupled Plasma) equipment and the etching gas is a mixtures gas of SF6, CF4, O2 and HBr.
Abstract translation: 目的：提供一种用于形成SAC（自对准接触）的栅极间隔物的方法，以改善SAC的开口裕度并增加垫的尺寸。 构成：导电图案（8,10）形成在半导体膜（2）上，并且在导电图案上形成氧化物膜。 在形成氧化膜（12）之后，栅极间隔物（14）沉积在氧化物和半导体膜上。 在栅极隔离物上涂覆光致抗蚀剂，通过以固定的蚀刻比蚀刻除去氧化膜。 残留的光致抗蚀剂通过灰化条纹化，并且栅极间隔物被回蚀刻。 光致抗蚀剂用作蚀刻栅极间隔物的蚀刻阻挡层。 在蚀刻光致抗蚀剂和氧化物膜的情况下，蚀刻工艺使用TCP（变压器耦合等离子体）设备，蚀刻气体是SF6，CF4，O2和HBr的混合气体。
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公开(公告)号：KR1020000073714A
公开(公告)日：2000-12-05
申请号：KR1019990017167
申请日：1999-05-13
Applicant: 삼성전자주식회사
IPC: H01L21/027 , G03F1/80
Abstract: PURPOSE: Provided is a formation method of contact hole for connection between metal wires, which prevents bowing phenomena and improves the problem of step coverage by forming contact hole as wine-glass shape. CONSTITUTION: The formation method of contact hole contains the step of; (i) forming insulated film(214) between layers on the board formed metal wires; (ii) depositing the photoresist film(216) on the insulated film(214); and (iii) forming contact hole(220) of which side wall is slopped on the insulated film(214) between layers by using photoresist pattern(216') as mask.
Abstract translation: 目的：提供金属线之间的连接接触孔的形成方法，通过形成作为酒杯形状的接触孔来防止弯曲现象并改善步骤覆盖的问题。 构成：接触孔的形成方法包括以下步骤： （i）在板上形成的金属线上的层之间形成绝缘膜（214）; （ii）将光致抗蚀剂膜（216）沉积在绝缘膜（214）上; 和（iii）通过使用光刻胶图案（216'）作为掩模，在层之间的绝缘膜（214）上形成侧壁的接触孔（220）。
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公开(公告)号：KR1020000056081A
公开(公告)日：2000-09-15
申请号：KR1019990005109
申请日：1999-02-12
Applicant: 삼성전자주식회사
IPC: H01L21/28
CPC classification number: H01L21/02164 , H01L21/02134 , H01L21/02304 , H01L21/02337 , H01L21/0234 , H01L21/02348 , H01L21/02351 , H01L21/02362 , H01L21/3124 , H01L21/76801
Abstract: PURPOSE: A method of fabricating a low dielectric constant interlayer insulating film is to minimize a parasitic capacitance between metal lines. CONSTITUTION: A fabrication method of a dielectric film comprises the steps of: forming a low dielectric constant dielectric film(210) including a hydrogen on an upper portion of a semiconductor substrate(200); and curing the low dielectric constant dielectric film by performing a plasma treatment(211). The plasma treatment is performed under a temperature in range of 50 to 1000°C and a pressure in range of 50 to 1000 mTorr by using a lamp(212) and a thermal supplying plate(213). Also, the plasma treatment comprises removing the hydrogen included in the dielectric film. The dielectric film including hydrogen has a Si-O-H structure and a dielectric constant of 4.0 below.
Abstract translation: 目的：制造低介电常数层间绝缘膜的方法是使金属线之间的寄生电容最小化。 构成：电介质膜的制造方法包括以下步骤：在半导体衬底（200）的上部形成包括氢的低介电常数电介质膜（210）; 并通过进行等离子体处理来固化低介电常数介电膜（211）。 使用灯（212）和供热板（213），在50〜1000℃的温度和50〜1000mTorr的压力范围内进行等离子体处理。 此外，等离子体处理包括去除包括在电介质膜中的氢。 包含氢的电介质膜具有Si-O-H结构，介电常数为4.0以下。
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