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公开(公告)号：KR100550344B1
公开(公告)日：2006-02-08
申请号：KR1020000001780
申请日：2000-01-14
Applicant: 삼성전자주식회사
Inventor： 고호
IPC: H01L21/306
Abstract: 애싱공정을 수행하는 동안 포토레지스트 층에서 파핑(popping) 현상이 발생하는 것을 방지할 수 있는 웨이퍼 애싱방법이 개시되어 있다. 포토레지스트 층이 형성된 웨이퍼를 가공 챔버 내부로 이송시키고, 웨이퍼 파지용 핀을 상승시켜 가공 챔버 내부로 이송된 상기 웨이퍼를 파지한다. 다음에, 진공 펌프를 가동시켜 상기 가공 챔버 내부를 진공화시킨 후, 상기 웨이퍼 파지용 핀을 서서히 하강시켜 상기 웨이퍼를 고온의 웨이퍼 지지대 상에 안착시킨다. 포토레지스트 층과 반응하는 가스를 상기 웨이퍼의 포토레지스트 층을 향해 분사시키고, RF 전류를 인가하여 상기 가스를 활성화시킨다. 설정된 시간이 경과한 후 가스 및 RF 전류의 공급을 중단하고, 상기 가공 챔버 내의 압력을 최저로 조정한 후 챔버 내의 압력을 질소로 정화시켜 상압으로 한다. 가공챔버 내부가 진공화된 상태에서 상기 웨이퍼 파지용 핀이 하강되므로 공기와의 마찰에 의해 웨이퍼가 옵셋 배치되는 것을 방지할 수 있고, 상기 웨이퍼 파지용 핀이 서서히 하강되므로, 급작스런 열교환으로 인해 포토레지스트 층에서 파핑현상이 발생하는 것을 방지할 수 있다.
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公开(公告)号：KR1020010057432A
公开(公告)日：2001-07-04
申请号：KR1019990060873
申请日：1999-12-23
Applicant: 삼성전자주식회사
Inventor： 고호
IPC: H01L21/66
Abstract: PURPOSE: An improved camera structure is provided to protect a camera lens for monitoring from a contamination source generated in a unit process to manufacture a semiconductor device. CONSTITUTION: The camera for monitoring a manufacturing procedure of a semiconductor device includes a lens(102) and a filter(104). The lens is composed of the quality of the material of a crystal series. The filter is composed of the quality of the material of a sapphire series to protect the lens from several contamination sources generated in a manufacturing procedure of a semiconductor device.
Abstract translation: 目的：提供一种改进的相机结构，以保护照相机镜头，以监视在单位过程中产生的污染源以制造半导体器件。 构成：用于监视半导体器件的制造程序的照相机包括透镜（102）和滤光片（104）。 透镜由水晶系列材料的质量组成。 滤光器由蓝宝石系列的材料的质量组成，以保护透镜免受在半导体器件的制造过程中产生的若干污染源。
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公开(公告)号：KR1020000056081A
公开(公告)日：2000-09-15
申请号：KR1019990005109
申请日：1999-02-12
Applicant: 삼성전자주식회사
IPC: H01L21/28
CPC classification number: H01L21/02164 , H01L21/02134 , H01L21/02304 , H01L21/02337 , H01L21/0234 , H01L21/02348 , H01L21/02351 , H01L21/02362 , H01L21/3124 , H01L21/76801
Abstract: PURPOSE: A method of fabricating a low dielectric constant interlayer insulating film is to minimize a parasitic capacitance between metal lines. CONSTITUTION: A fabrication method of a dielectric film comprises the steps of: forming a low dielectric constant dielectric film(210) including a hydrogen on an upper portion of a semiconductor substrate(200); and curing the low dielectric constant dielectric film by performing a plasma treatment(211). The plasma treatment is performed under a temperature in range of 50 to 1000°C and a pressure in range of 50 to 1000 mTorr by using a lamp(212) and a thermal supplying plate(213). Also, the plasma treatment comprises removing the hydrogen included in the dielectric film. The dielectric film including hydrogen has a Si-O-H structure and a dielectric constant of 4.0 below.
Abstract translation: 目的：制造低介电常数层间绝缘膜的方法是使金属线之间的寄生电容最小化。 构成：电介质膜的制造方法包括以下步骤：在半导体衬底（200）的上部形成包括氢的低介电常数电介质膜（210）; 并通过进行等离子体处理来固化低介电常数介电膜（211）。 使用灯（212）和供热板（213），在50〜1000℃的温度和50〜1000mTorr的压力范围内进行等离子体处理。 此外，等离子体处理包括去除包括在电介质膜中的氢。 包含氢的电介质膜具有Si-O-H结构，介电常数为4.0以下。
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公开(公告)号：KR1020000052110A
公开(公告)日：2000-08-16
申请号：KR1019990002966
申请日：1999-01-29
Applicant: 삼성전자주식회사
IPC: H01L21/306
Abstract: PURPOSE: A method for etching an etch stopping layer of a self-aligned contact is to reduce a contact resistance and to improve a refresh characteristics of a device. CONSTITUTION: An etching method of an etch stopping layer of a self-aligned contact comprises the steps of: including a conductive layer pattern(8) covered with a first substance layer(10,12) on a semiconductor substrate(2); and etching an interlayer insulation layer(16) between the neighboring conductive layer pattern, and a second substance layer(14) formed under the insulation layer so as to form a contact hole, the second substance layer being an etch stopping layer when the interlayer insulation layer is etched using a down stream chamber.
Abstract translation: 目的：蚀刻自对准接触的蚀刻停止层的方法是减小接触电阻并改善器件的刷新特性。 构造：自对准接触的蚀刻停止层的蚀刻方法包括以下步骤：包括在半导体衬底（2）上覆盖有第一物质层（10,12）的导电层图案（8）; 以及蚀刻相邻的导电层图案之间的层间绝缘层（16）和形成在所述绝缘层之下的第二物质层（14）以形成接触孔，所述第二物质层当所述层间绝缘 使用下游室蚀刻层。
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公开(公告)号：KR1020000008052A
公开(公告)日：2000-02-07
申请号：KR1019980027698
申请日：1998-07-09
Applicant: 삼성전자주식회사
IPC: H01L21/306
Abstract: PURPOSE: A plasma etching apparatus is provided to improve a throughput by minimizing a generation of error due to reverse inflow of plasma and by improving holes structure of an orifice ring. CONSTITUTION: The plasma etching apparatus comprises a tube(40). The tube(40) includes an orifice ring(42) formed at sides of inlet to inflow reaction gas from a gas cap(14). The diameter of hole of the orifice ring(42) is more narrow than that of the gas cap(14). Thereby, when plasma formation, the reverse inflow of the generated plasma is minimized. The thickness of the orifice ring(42) has 2 millimeters more than. The orifice ring(42) includes a first orifice ring(92) formed at edge portion of the tube(40) and a second orifice ring(94) formed in the tube(40).
Abstract translation: 目的：提供等离子体蚀刻装置，通过最小化由于等离子体的反向流入导致的误差的产生以及改善孔环的孔结构来提高生产率。 构成：等离子体蚀刻装置包括管（40）。 管（40）包括形成在入口侧的来自气帽（14）的反应气体的孔环（42）。 孔环（42）的孔直径比气盖（14）的直径更窄。 因此，当等离子体形成时，所产生的等离子体的反向流入最小化。 孔环（42）的厚度大于2毫米。 孔环（42）包括形成在管（40）的边缘部分处的第一孔环（92）和形成在管（40）中的第二孔环（94）。
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Patent Agency Ranking
公开(公告)号：KR100564546B1
公开(公告)日：2006-03-28
申请号：KR1019990012036
申请日：1999-04-07
Applicant: 삼성전자주식회사
IPC: H01L21/205
Abstract: 본 발명의 저유전율막의 증착 설비는, 저유전율막이 증착될 또는 증착된 반도체 웨이퍼를 로딩 또는 언로딩시키는 로딩/언로딩부와, 그 로딩/언로딩부에 의해 로딩된 반도체 웨이퍼상에 저유전율막을 도포하는 제1 챔버와, 도포된 저유전율막을 베이크하는 제2 챔버와, 베이크 공정을 마친 저유전율막의 결합 구조를 저유전율막의 특성을 유지시키면서 변경시키는 제3 챔버를 포함한다.
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公开(公告)号：KR100519543B1
公开(公告)日：2005-12-08
申请号：KR1019980027698
申请日：1998-07-09
Applicant: 삼성전자주식회사
IPC: H01L21/306
Abstract: 본 발명은 튜브가 구비되는 반도체소자 제조용 플라즈마 식각장치에 관한 것이다. 본 발명은, 플라즈마를 형성시키기 위한 반응가스가 가스캡으로부터 유입되도록 상기 반응가스가 유입되는 측면으로 홀이 형성되는 오리피스링이 구비되는 튜브 등으로 이루어지는 반도체소자 제조용 플라즈마 식각장치에 있어서, 상기 오리피스링은 상기 홀의 직경을 상기 반응가스를 유입시키는 측면의 가스캡의 홀의 직경보다 협소하게 형성시켜 상기 튜브에 구비시키는 것을 특징으로 한다. 따라서, 플라즈마 식각장치를 이용한 식각공정의 수행시 발하는 플라즈마의 역유입으로 인한 불량의 발생을 최소화시킴으로써 반도체소자의 제조에 따른 생산성이 향상되는 효과가 있다.
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公开(公告)号：KR1020010073411A
公开(公告)日：2001-08-01
申请号：KR1020000001780
申请日：2000-01-14
Applicant: 삼성전자주식회사
Inventor： 고호
IPC: H01L21/306
Abstract: PURPOSE: A method for ashing a wafer is provided to reduce a popping phenomenon of a photoresist layer and stably arrange wafers on exact positions of supports. CONSTITUTION: A wafer on which a photoresist layer is formed is transported to an inside of a processing chamber. A wafer holding pin is upraised and holds the wafer transported into the inside of the processing chamber. A vacuum pump makes vacuum the inside of the processing chamber. The wafer holding pin is slowly lowered within the vacuum processing chamber and stably puts the wafer on a wafer support of high temperature. A gas reacting with the photoresist layer is injected to the photoresist layer of the wafer. An RF current is applied to activate the gas. After a predetermined period of time is passed, supply of gas and RF current is stopped. A pressure within the processing chamber is controlled to become the lowest. The inside of the processing chamber is purged with nitrogen, thereby increasing the pressure.
Abstract translation: 目的：提供一种用于灰化晶片的方法，以减少光致抗蚀剂层的弹出现象，并将晶片稳定地布置在支撑体的精确位置上。 构成：其上形成有光致抗蚀剂层的晶片被输送到处理室的内部。 提升晶片保持销并将晶片保持在运送到处理室的内部。 真空泵在处理室内部进行真空。 晶片保持销在真空处理室内缓慢降低，并将晶片稳定地放置在高温晶片支架上。 与光致抗蚀剂层反应的气体被注入晶片的光致抗蚀剂层。 施加RF电流以激活气体。 经过一段预定的时间后，停止供气和射频电流。 处理室内的压力被控制成最低。 处理室的内部用氮气吹扫，从而增加压力。
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公开(公告)号：KR1020030078592A
公开(公告)日：2003-10-08
申请号：KR1020020034312
申请日：2002-06-19
Applicant: 삼성전자주식회사
IPC: H01L21/205
Abstract: PURPOSE: An electrode assembly for processing a semiconductor substrate and a processing apparatus having the same are provided to prevent the arc discharge generated between electrodes and connecting parts by using a bolt as the connecting part. CONSTITUTION: An electrode assembly for processing a semiconductor substrate is provided with the first electrode(202) connected with a high frequency power supply used for transforming the processing gas of the semiconductor substrate into plasma, the second electrode(204) located at the first surface of the first electrode, and the first connecting part made of the first material having the first conductivity, located for connecting the first electrode with the second electrode. Preferably, the first and second electrode are made of aluminum and the first material is one selected from a group consisting of silver, copper, gold, and aluminum. Preferably, the first connecting part includes a bolt(208) made of the first material.
Abstract translation: 目的：提供一种用于处理半导体衬底的电极组件和具有该电极组件的处理设备，以通过使用螺栓作为连接部分来防止电极和连接部件之间产生的电弧放电。 构成：用于处理半导体衬底的电极组件设置有与用于将半导体衬底的处理气体转换成等离子体的高频电源连接的第一电极（202），位于第一表面的第二电极 以及由具有第一导电性的第一材料制成的第一连接部，用于将第一电极与第二电极连接。 优选地，第一和第二电极由铝制成，第一材料是选自银，铜，金和铝的一种。 优选地，第一连接部件包括由第一材料制成的螺栓（208）。
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公开(公告)号：KR1020020057357A
公开(公告)日：2002-07-11
申请号：KR1020010000348
申请日：2001-01-04
Applicant: 삼성전자주식회사
Inventor： 고호
IPC: H01L21/68
Abstract: PURPOSE: A wafer transfer arm is provided to endure long periods of high and low temperature and achieve simplification. CONSTITUTION: The wafer transfer arm(100) comprises a blade link part(110) controlled by a motor and blade arm(120) which has a shape of a plate and holds a wafer(200). A connecting hole(129) for a screw is formed on the blade arm and the blade link part. The blade arm has a vacuum line, a vacuum hole(124) for adsorbing a wafer and a plurality of circle-type through holes(126). The through holes(126) is a structure for minimizing the load which is transferred from the blade link part to the arm and for minimizing heat-transfer from the wafer during a time of holding the wafer in a high temperature.
Abstract translation: 目的：提供晶圆传送臂以承受长时间的高温和低温并实现简化。 构成：晶片传送臂（100）包括由马达和刀臂（120）控制的刀片连接部分（110），其具有板的形状并保持晶片（200）。 用于螺钉的连接孔（129）形成在刀臂和刀片连杆部分上。 刀臂具有真空管线，用于吸附晶片的真空孔（124）和多个圆形通孔（126）。 通孔（126）是用于最小化从刀片连接部分转移到臂上的负载并且在将晶片保持在高温期间最小化从晶片的热传递的结构。
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