Abstract:
PURPOSE: An incremental delta-sigma analog to digital converter and devices having the same are provided to generate an operand by using a down counter implementing the down count operation in response to the clock signal. CONSTITUTION: A delta-sigma analog to digital converter comprises a delta-sigma modulator(12), an operand generator(18-1), and a selecting circuit(14-1). The operand generator generates the operand in response to the clock signal. A selection circuit selectively transmits the operand to an adder(16) according to the output value outputted from the delta-signal modulator in response to the clock signal.
Abstract:
스위치드-커패시터적분기가개시된다. 상기스위치드-커패시터적분기는제1클락페이즈에서입력신호를샘플링하고제2클락페이즈에서샘플된입력신호를자신의증폭기를이용하여적분하고리셋동작시마다상기증폭기의입력단의전압을일정한리셋전압으로리셋시킨다. 상기리셋전압은상기증폭기의오프셋전압또는외부로부터공급된정전압일수 있다.
Abstract:
A ramp generator and a ramp signal generating method thereof are provided to generate a ramp signal of a proper index function even if the characteristic change of the detector occurs by calibrating inclination and curvature of the ramp signal in real time using a calibration circuit. A ramp generator(20) comprises a ramp signal generating circuit(100), and a calibration circuit(200). The ramp signal generating circuit generates a ramp signal which increases as an index function. The ramp signal generating circuit receives the ramp signal and calibrates inclination and curvature of the ramp signal in real time. The calibration circuit calibrates the ramp signal by comparing voltage differences between the ramp signal and a target ramp signal. The ramp signal generating circuit includes an OP amplifier, a resistor(R), a capacitor(C), a feedback resistor(Rf), and a variable resistor(Rv). A switch(Sw) is placed between an inversion input end of the OP amplifier and an output end of the OP amplifier.