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1.发明授权
公开(公告)号：KR101633283B1
公开(公告)日：2016-06-24
申请号：KR1020090088755
申请日：2009-09-18
Applicant: 삼성전자주식회사
IPC: H04N5/335 , H01L27/146
CPC classification number: H04N5/3575 , H04N5/374 , H04N5/378
Abstract: 상관이중샘플링회로가제공된다. 상기상관이중샘플링회로는 CDS 페이즈동안에리셋신호와이미지신호각각에대하여 CDS를수행하고 CDS된리셋신호와 CDS된이미지신호의차이를출력하기위한샘플링회로, 및 PGA 페이즈동안에상기샘플링회로로부터출력되는상기차이를상기샘플링회로의입력으로피드백하기위한피드백유닛을포함한다.
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公开(公告)号：KR101700371B1
公开(公告)日：2017-01-26
申请号：KR1020100064090
申请日：2010-07-02
Applicant: 삼성전자주식회사
IPC: H04N5/335
Abstract: 이중상관샘플링회로가개시된다. 상기상관이중샘플링회로는입력신호를수신하고, 상기입력신호를디지털신호로델타-시그마변조하여모듈레이션신호를출력하는델타-시그마모듈레이터; 동작페이즈에따른선택신호에응답하여상기모듈레이션신호를출력하거나상기모듈레이션신호를반전시킨반전신호를출력하는선택회로: 및제1 동작페이즈에서는상기모듈레이션신호및 상기반전신호중 어느하나에대한누산동작을수행하고, 제2 동작페이즈에서는상기제1 동작페이즈에서의누산결과에상기모듈레이션신호및 상기반전신호중 나머지하나에대한누산동작을수행하는누산회로를포함할수 있다.
Abstract translation: 相关双采样电路包括Δ-Σ调制器，选择电路和累积电路。 Δ-Σ调制器被配置为接收输入信号，Δ-Σ调制输入信号，并输出调制信号。 选择电路被配置为响应于对应于操作阶段的选择信号，反转调制信号并选择性地输出调制信号和反相调制信号中的一个。 累积电路被配置为通过在第一操作阶段中对调制信号和反相调制信号之一执行累加处理来产生第一累加结果，并且通过对第一累积结果执行累积处理来生成第二累加结果，以及 在第二操作阶段中的另一个调制信号和反相调制信号。
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公开(公告)号：KR101634359B1
公开(公告)日：2016-06-28
申请号：KR1020090090197
申请日：2009-09-23
Applicant: 삼성전자주식회사
Abstract: 클럭신호의변화를통하여이득을제어하는아날로그-디지털컨버터및 이를포함하는이미지센서가개시된다. 본발명의아날로그-디지털컨버터는입력신호및 클럭신호를입력받아상기클럭신호에기초하여클럭신호에응답하여, 입력신호를시그마-텔타변조신호로변조하여변조된디지털출력신호를출력하는시그마-델타모듈레이터(modulator); 및아날로그- 디지털변환시간에맞추어상기클럭신호의주기마다상기디지털출력신호를누산하여얻은누산출력값을출력하는누산기(accumulator)를포함하며, 상기아날로그-디지털변환시간에포함되는상기클럭신호의클럭수를가변함으로써그 이득이가변된다.
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公开(公告)号：KR1020130101209A
公开(公告)日：2013-09-13
申请号：KR1020120022163
申请日：2012-03-05
Applicant: 삼성전자주식회사
CPC classification number: G11C7/06 , G11C7/10 , G11C7/1033 , G11C7/1051 , G11C7/22 , G11C19/00 , G11C27/02 , H01L27/146 , H01L27/14634 , H01L27/14643
Abstract: PURPOSE: A line memory and a CMOS image integrated circuit device using the same read out data of the line memory at high speed by a read clock signal shorter than the maximum delay time. CONSTITUTION: Multiple memory cells (152) are adjacent to each other and arranged in a row. One sense amplifier (154) is provided. A pair of data lines (156) connects the multiple memory cells and the sense amplifier and transmits data stored in each memory cell to the sense amplifier with different lengths of delay time. A data output unit (158) is connected to an output terminal of the sense amplifier and continuously outputs data in order of the arrangement of the multiple memory cells by synchronizing with a read clock signal shorter than the maximum delay time among the different lengths of delay time.
Abstract translation: 目的：一种线路存储器和CMOS图像集成电路器件，通过比最大延迟时间短的读取时钟信号，以高速读出行存储器的数据。 构成：多个存储器单元（152）彼此相邻并排成一行。 提供一个读出放大器（154）。 一对数据线（156）连接多个存储器单元和读出放大器，并将存储在每个存储单元中的数据传送到具有不同长度的延迟时间的读出放大器。 数据输出单元（158）连接到读出放大器的输出端，并通过与延迟时间不同的延迟时间短的读时钟信号同步地连续输出多个存储单元的配置顺序的数据 时间。
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公开(公告)号：KR1020130058977A
公开(公告)日：2013-06-05
申请号：KR1020110125020
申请日：2011-11-28
Applicant: 삼성전자주식회사
IPC: H04N5/361
Abstract: PURPOSE: An offset removal circuit and an image sensor including the same are provided to remove a dark current offset which can be generated in a unit pixel by using a different reference signal according to the operation section of the unit pixel. CONSTITUTION: A feedback circuit(130) is connected to a second electrode of a decoupling capacitor(110) and an output terminal of a buffer(120) and respectively receives a first reference voltage and a second reference voltage in a reset section and a data section. In order to charge the decoupling capacitor with a first voltage which is a voltage difference of a reset voltage and the first reference voltage in the reset section, the feedback circuit provides the first reference voltage to the second electrode and provides the second reference voltage to the second electrode in the data section.
Abstract translation: 目的：提供偏移消除电路和包括该偏移消除电路的图像传感器，以通过使用根据单位像素的操作部分的不同参考信号去除可以在单位像素中产生的暗电流偏移。 构成：反馈电路（130）连接到去耦电容器（110）的第二电极和缓冲器（120）的输出端子，并分别在复位部分和数据中接收第一参考电压和第二参考电压 部分。 为了对具有复位电压的电压差的第一电压和复位部分中的第一参考电压对去耦电容器充电，反馈电路将第一参考电压提供给第二电极，并将第二参考电压提供给 第二电极在数据部分。
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Patent Agency Ranking
公开(公告)号：KR1020120081426A
公开(公告)日：2012-07-19
申请号：KR1020110002764
申请日：2011-01-11
Applicant: 삼성전자주식회사
CPC classification number: H03M1/164 , H03M1/50 , H03M3/424 , H03M3/456 , H03M3/458 , H04N5/378 , H03M1/12 , H04N5/3698
Abstract: PURPOSE: An analog digital converter and an image sensor including the same are provided to implement high speed, high resolution, and low power of an image sensor. CONSTITUTION: A pixel array(110) is arranged in a matrix shape. The pixel array includes a plurality of pixels(111). An EC-ADC(Extended Analog Digital Converter)(140) performs first analog digital conversion for converting an output signal of the pixel array into a digital signal. The EC-ADC obtains residue by using the output signal of the pixel array. The EC-ADC performs second analog digital conversion by using the residue.
Abstract translation: 目的：提供一个模拟数字转换器和包含该模拟数字转换器的图像传感器，以实现图像传感器的高速，高分辨率和低功耗。 构成：像素阵列（110）以矩阵形状排列。 像素阵列包括多个像素（111）。 EC-ADC（扩展模拟数字转换器）（140）执行用于将像素阵列的输出信号转换为数字信号的第一模拟数字转换。 EC-ADC通过使用像素阵列的输出信号来获得残差。 EC-ADC通过使用残留物进行第二次模拟数字转换。
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公开(公告)号：KR1020120041849A
公开(公告)日：2012-05-03
申请号：KR1020100103205
申请日：2010-10-22
Applicant: 삼성전자주식회사
CPC classification number: H04N5/378 , H03M1/162 , H03M1/56 , H04N5/3575 , H04N5/374
Abstract: PURPOSE: An analog to digital converter and an image sensor including the same are provided to reduce the drive capacitance of a lamp signal generating unit by generating a comparison signal in a first comparison mode and a second comparison mode. CONSTITUTION: An analog to digital converter(1000) comprises a comparison signal generation unit(1100) and a control unit(1200). The analog to digital converter is operated in a first comparison mode and a second comparison mode. The analog to digital converter roughly compares input signals in the first comparison mode. The analog digital converter precisely compares the input signals in the second comparison mode. The comparison signal generator compares the input signal with a selection reference signal in the first comparison mode. The comparison signal generator compares a differential voltage with a lamp signal in the second comparison mode.
Abstract translation: 目的：提供一种模拟数字转换器和包括该模数转换器的图像传感器，以通过在第一比较模式和第二比较模式中生成比较信号来降低灯信号生成单元的驱动电容。 构成：模拟数字转换器（1000）包括比较信号生成单元（1100）和控制单元（1200）。 模数转换器在第一比较模式和第二比较模式下操作。 模数转换器粗略地比较第一比较模式下的输入信号。 模拟数字转换器精确地比较第二比较模式下的输入信号。 比较信号发生器在第一比较模式下将输入信号与选择参考信号进行比较。 比较信号发生器将第二比较模式中的差分电压与灯信号进行比较。
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公开(公告)号：KR1020110021426A
公开(公告)日：2011-03-04
申请号：KR1020090079218
申请日：2009-08-26
Applicant: 삼성전자주식회사
IPC: H03M1/12
Abstract: PURPOSE: An analog-to-digital converter and an image processing devices having the same are provided to efficiently reduce an off-set component which is generated from an amplifier by using a correlated double sampling circuit and a delta-sigma analog digital converter. CONSTITUTION: In an analog-to-digital converter and an image processing devices having the same, a correlated double sampling circuit(110) outputs a correlated double sampling rest signal and correlated double sampling image signal by performing correlated double sampling of the reset signal and the image signal form a pixel respectively. A delta-sigma analog digital converter(120) generates a first digital code by converting a correlated double sampled reset signal to a delta-sigma analog-digital. The delta-sigma analog digital converter(120) generates a second digital code by converting the correlated double sampled reset signal to a delta-sigma analog-digital. The delta-sigma analog digital converter outputs the difference between the first digital code and the second digital code.
Abstract translation: 目的：提供一种模拟 - 数字转换器和具有该模拟数字转换器的图像处理装置，以通过使用相关的双采样电路和Δ-Σ模拟数字转换器来有效地减少从放大器产生的偏移分量。 构成：在模拟数字转换器和具有该数字转换器的图像处理装置中，相关双重采样电路（110）通过执行复位信号的相关双重采样来输出相关的双采样静止信号和相关的双采样图像信号，以及 图像信号分别形成像素。 Δ-Σ模拟数字转换器（120）通过将相关的双采样复位信号转换为Δ-Σ模拟数字来产生第一数字码。 Δ-Σ模拟数字转换器（120）通过将相关的双采样复位信号转换成Δ-Σ模拟数字来产生第二数字码。 Δ-Σ模拟数字转换器输出第一数字码和第二数字码之间的差值。
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公开(公告)号：KR101758310B1
公开(公告)日：2017-07-27
申请号：KR1020110002764
申请日：2011-01-11
Applicant: 삼성전자주식회사
Abstract: 본발명에따른이미지센서는복수의행과복수의열을갖는매트릭스형상으로배열되며, 각각이입사광세기를전기적인영상신호로변환하여출력하는복수의화소들을포함하는화소어레이; 및상기화소어레이의출력신호를디지털신호로변환하는제1 아날로그디지털변환을수행하고, 상기화소어레이의출력신호및 상기디지털신호를이용하여레지듀(residue)를얻고, 상기레지듀를이용하여제2 아날로그디지털변환을수행하는확장아날로그디지털컨버터를포함한다.
Abstract translation: 根据本发明的图像传感器被布置在具有多个行和多个列，像素阵列，其每一个包括多个用于转换和输出该入射光强度成电图象信号的像素矩阵; 并且执行用于将像素阵列的输出信号转换为数字信号的第一模数转换，使用像素阵列的输出信号和数字信号获得残差， 2模数转换。
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公开(公告)号：KR101648066B1
公开(公告)日：2016-08-12
申请号：KR1020100103205
申请日：2010-10-22
Applicant: 삼성전자주식회사
CPC classification number: H04N5/378 , H03M1/162 , H03M1/56 , H04N5/3575 , H04N5/374
Abstract: 아날로그-디지털컨버터는비교신호발생부및 제어부를포함한다. 비교신호발생부는스위치제어신호에기초하여, 제1 비교모드에서입력신호를상기선택기준신호와비교하고제2 비교모드에서파인전압레벨보다작아지도록상기입력신호로부터변환된차전압을램프신호와비교하여비교신호를생성한다. 제어부는상기비교신호및 모드선택신호에기초하여상기스위치제어신호를생성한다.
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