Abstract:
A method for manufacturing a semiconductor device is provided to enhance reliability by preventing the generation of noise of an image sensor. An interlayer dielectric(120) is formed on a substrate(100) including a gate insulating layer(105), a gate electrode, and a photodiode region(118). A mold insulating layer is formed on the interlayer dielectric in order to expose the interlayer dielectric on the photodiode region. A protective layer(185) including hydrogen atoms are formed along a profile of the mold insulating layer. An annealing process is performed to diffuse the hydrogen atoms from the protective layer to the gate insulating layer and the photodiode region.
Abstract:
A method for fabricating an image sensor is provided to reduce random noise by including a gate insulation layer formed in an active region such that the gate insulation layer is made of an oxide material. A semiconductor substrate(100) is prepared which has first, second and third regions. A photodiode(104) is formed on the surface of the substrate in the first region. A first gate insulation layer(108) is formed on the first region, adjacent to the photodiode. A first gate electrode(112) is formed on the first gate insulation layer while a first electrode(116) of a capacitor is formed on the third region. A dielectric layer(118) is formed on the lateral surfaces of the first electrode of the capacitor. A second gate insulation layer(122) is formed in the second region of the substrate. A second gate electrode(126) is formed on the second gate insulation layer while a second electrode(128) of the capacitor electrically connected to the first electrode of the capacitor is formed on the third region by interposing the dielectric layer. Spacers can be formed on the sidewalls of the first and second gate electrodes, respectively.
Abstract:
두 종류의 소자분리영역을 포함하는 씨모스(CMOS) 이미지 센서 및 그 제조 방법이 제공된다. 본 발명에 따른 CMOS 이미지 센서는, 포토다이오드가 형성되는 활성영역의 적어도 일 측면을 둘러싸는 불순물 도핑으로 형성된 소자분리영역과, 그 위에 제어 게이트들이 형성되는 활성영역과 포토다이오드가 형성되는 활성영역의 일부를 둘러싸는 절연층으로 형성된 소자분리영역을 포함한다.
Abstract:
A CMOS image sensor is provided to remarkably reduce a surface defect of a substrate having a photoelectric transformation device by using a non nitrous acid source in forming an oxide layer in contact with the photoelectric transformation device. A photoelectric transformation device(62) transforms a light signal into an electrical signal, formed in a semiconductor substrate. A transistor processes the electrical signal transformed by the photoelectric transformation device. An insulation layer in contact with the photoelectric transformation device is a pure oxide layer. A floating diffusion layer(56) is formed in the semiconductor substrate. A transfer gate electrode(52) transfers the electrical signal of the photoelectric transformation device to the floating diffusion layer, formed on the substrate between the photoelectric transformation device and the floating diffusion layer. A gate spacer(64) is formed on the sidewall of the transfer gate electrode. The gate space is a pure oxide layer.
Abstract:
A CMOS image sensor and a manufacturing method thereof are provided to prevent the generation of cross-talk between adjacent pixels by using an improved light shielding pattern with a heat resisting capability. A CMOS image sensor comprises a semiconductor substrate(100) with a photodiode(120) and a transistor, an interlayer dielectric on the semiconductor substrate, and a light shielding pattern. The light shielding pattern(142) is formed on the interlayer dielectric. The light shielding pattern encloses a peripheral portion of the photodiode. The light shielding pattern is made of one selected from a group consisting of a tungsten layer, a titanium layer, a nitride titanium layer, and a stacked structure of the titanium and nitride titanium layers.
Abstract:
PURPOSE: A trench isolation method is provided to prevent a dent phenomenon chronically occurring in a conventional trench-type isolation process by performing a relatively simple additional process for recessing a pad layer. CONSTITUTION: The pad layer is formed on a substrate(100). An etch stop layer is formed on the pad layer. The etch stop layer, the pad layer and the substrate in a trench region are sequentially eliminated through a patterning process to form an etch stop layer pattern, a pad layer pattern and a substrate trench(140). An isotropic etch process is performed on the pad layer pattern to laterally recess the pad layer pattern. A silicon nitride layer liner(160) is formed on the substrate including the inner wall of the trench. A silicon oxide layer is stacked on the substrate to fill the trench. A chemical mechanical polishing(CMP) process is performed on the front surface of the substrate until the etch stop layer pattern is exposed. The etch stop layer pattern is removed to expose an active region through an etch process.
Abstract:
본 발명은 복합 반도체 장치의 비대칭 게이트 산화막 제조 방법에 관한 것으로서, 특히 상기 DRAM 영역보다 로직회로 영역의 게이트 산화막이 더 두껍게 형성되도록 제조하는 것을 특징으로 한다. 따라서, 본 발명은 DRAM의 대용량화와 로직회로의 고속성을 각각 달성할 수 있기 때문에 원칩의 성능 및 신뢰성을 향상시킬 수 있다.