公开(公告)号：KR100459698B1

公开(公告)日：2004-12-04

申请号：KR1020020007531

申请日：2002-02-08

Applicant: 삼성전자주식회사

Inventor： 고길영 ,  방정호 ,  초종복

IPC: G11C29/00

CPC classification number: G01R31/31926

Abstract: A method of electrically testing a semiconductor device preferably includes connecting a common input/output signal channel (line) of a socket board to two or more data pins of the semiconductor device. Signals output from the semiconductor device may be sequentially read via the short-circuited input/output signal lines of the socket board by carrying out a byte operation function. The throughput of a semiconductor test system can thereby be increased by increasing the number of devices that can be tested in parallel.

Abstract translation: 电测试半导体器件的方法优选地包括将插座板的公共输入/输出信号通道（线路）连接到半导体器件的两个或更多数据管脚。 通过执行字节操作功能，可以通过插座板的短路输入/输出信号线顺序读取从半导体器件输出的信号。 因此可以通过增加可以并行测试的器件的数量来增加半导体测试系统的吞吐量。

公开(公告)号：KR1020040066553A

公开(公告)日：2004-07-27

申请号：KR1020030003648

申请日：2003-01-20

Applicant: 삼성전자주식회사

Inventor： 윤금진 ,  정진성 ,  강성구 ,  방정호 ,  민병준

IPC: H01L21/66

CPC classification number: G01R31/287 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: PURPOSE: An integrated monitoring burn-in test method for multi-chip package is provided to shorten an interval of a burn-in test and reduce a probability of error occurrence caused by an operator by converting an individual burn-in test into an integrated burn-in test. CONSTITUTION: A multi-chip package into which various kinds of semiconductor devices are integrated is loaded into a chamber of a burn-in apparatus capable of applying at least two scan control signals(P102). An integrated burn-in program capable of testing the multi-chip package is loaded into the burn-in apparatus(P104). A burn-in test is performed on the multi-chip package by using the integrated burn-in program(P114).

Abstract translation: 目的：提供多芯片封装的综合监控老化测试方法，缩短老化测试的间隔时间，并通过将单独的老化测试转换为一体式烧录，降低操作员造成的错误发生概率 在测试 构成：将各种半导体器件集成到其中的多芯片封装被加载到能够施加至少两个扫描控制信号的老化装置的腔室（P102）中。 能够测试多芯片封装的集成老化程序被加载到老化装置（P104）中。 通过使用集成的烧录程序（P114），在多芯片封装上进行老化测试。

公开(公告)号：KR100440971B1

公开(公告)日：2004-07-21

申请号：KR1020020040406

申请日：2002-07-11

Applicant: 삼성전자주식회사

Inventor： 방정호

IPC: G09G3/296

Abstract: PURPOSE: A Y-driver for plasma display panel is provided to simplify a structure and reduce manufacturing costs by excluding a switching device to switch the large amount of current between a Y-electrode and an energy recovery circuit. CONSTITUTION: A Y-driver for plasma display panel includes the first switch(Ys), an integral circuit, the second switch(Ys1), and the third switch(Yrr). The first switch(Ys) is used for switching a scan voltage. The integral circuit is serially connected between the reset voltage and the first switch(Ys) in order to form a rising period of a ramp pulse in a reset period. The second switch(Ys1) is inserted between a contact point between the first switch(Ys) and the integral circuit and a Y-electrode. The third switch(Yrr) is inserted between an output terminal for an integral voltage of the integral circuit and the Y-electrode. The first switch(Ys) is turned on in the rising period of the ramp pulse and turned off in a falling period of the ramp pulse. The second switch(Ys1) and the third switch(Yrr) is turned off in the rising period of the ramp pulse and turned on in the falling period of the ramp pulse.

Abstract translation: 目的：提供用于等离子显示面板的Y驱动器，通过排除开关器件以切换Y电极和能量恢复电路之间的大量电流来简化结构并降低制造成本。 构成：用于等离子体显示面板的Y驱动器包括第一开关（Ys），积分电路，第二开关（Y​​s1）和第三开关（Yrr）。 第一开关（Ys）用于切换扫描电压。 积分电路串联连接在复位电压与第一开关（Ys）之间，以在复位周期中形成斜坡脉冲的上升周期。 第二开关（Y​​s1）插入在第一开关（Ys）和积分电路之间的接点和Y电极之间。 第三开关（Yrr）插在积分电路的积分电压输出端和Y电极之间。 第一个开关（Ys）在斜坡脉冲的上升周期内导通，在斜坡脉冲的下降周期内关断。 第二开关（Y​​s1）和第三开关（Yrr）在斜坡脉冲的上升周期内关闭，并在斜坡脉冲的下降周期内开启。

公开(公告)号：KR1020040001017A

公开(公告)日：2004-01-07

申请号：KR1020020036073

申请日：2002-06-26

Applicant: 삼성전자주식회사

Inventor： 정진성 ,  윤금진 ,  방정호 ,  최상영 ,  박동규 ,  김낙문

IPC: G11C29/00 ,  G01R31/26 ,  H01L21/66

Abstract: PURPOSE: A test method of a multi-chip package using a monitor burn-in tester is provided to reduce test time and increase test efficiency. CONSTITUTION: A multi-chip package having at least two semiconductor devices, is tested by using a monitor burn-in tester. One test program is used for carrying out the multi-chip package test. Each semiconductor device is sequentially carried out with the test after contacting a plurality of test pins to the semiconductor devices(100,200,400,600). The test program has a multiplexer control function capable of selecting all the multiplexer functions included to the semiconductor devices. The test program includes an input/output masking function for masking the input/output port of a test board unused by the different input/output ports of the semiconductor devices.

Abstract translation: 目的：提供使用监视器老化测试仪的多芯片封装的测试方法，以减少测试时间并提高测试效率。 构成：通过使用监视器老化测试仪测试具有至少两个半导体器件的多芯片封装。 一个测试程序用于进行多芯片封装测试。 在将多个测试引脚接触到半导体器件（100,200,400,600）之后，通过测试顺序地执行每个半导体器件。 测试程序具有多路复用器控制功能，能够选择包括在半导体器件中的所有多路复用器功能。 测试程序包括用于屏蔽由半导体器件的不同输入/输出端口使用的测试板的输入/输出端口的输入/输出屏蔽功能。

公开(公告)号：KR1020030091532A

公开(公告)日：2003-12-03

申请号：KR1020020029613

申请日：2002-05-28

Applicant: 삼성전자주식회사

Inventor： 김환석 ,  신경선 ,  방정호

IPC: G06F15/16

Abstract: PURPOSE: A computer network system and a method for according time between a server computer and a client computer on the same are provided to accord the time between the server computer and the client computer. CONSTITUTION: The server(510) comprises a time information transmitting circuit(511) and a time setting command circuit(512). The time information transmitting circuit transmits the time information of the server to the client by responding to a time information request received when the client is started. The time setting command circuit transmits a command to make the client set the time information of the server after a constant time. The client(520) comprises a time information command circuit(521) and a time information setting circuit(522). The time information command circuit transmits the command to accord the time of the client with the time of the server when the client is started. The time information setting circuit sets the time information to the client by responding to the command of the time setting command circuit after the constant time.

Abstract translation: 目的：提供计算机网络系统和服务器计算机与客户端计算机之间根据时间的方法，以使服务器计算机与客户端计算机之间的时间一致。 构成：服务器（510）包括时间信息发送电路（511）和时间设定指令电路（512）。 时间信息发送电路通过响应客户端启动时收到的时间信息请求，将服务器的时间信息发送给客户端。 时间设定指令电路发送命令，使得客户机在一定时间之后设置服务器的时间信息。 客户端（520）包括时间信息命令电路（521）和时间信息设置电路（522）。 当客户端启动时，时间信息命令电路发送符合客户端时间的命令与服务器的时间。 时间信息设定电路在恒定时间后响应时间设定指令电路的指令，将时间信息设定在客户端。

公开(公告)号：KR1020030050663A

公开(公告)日：2003-06-25

申请号：KR1020010081161

申请日：2001-12-19

Applicant: 삼성전자주식회사

Inventor： 권혁 ,  방정호 ,  심현섭 ,  김용운 ,  이형영 ,  신영구

IPC: G11C29/00

CPC classification number: G11C29/26 ,  G11C2029/2602

Abstract: PURPOSE: A parallel test system of a DUT(Device Under Test) is provided to increase the number of the DUTs in a parallel test process by using the limited number of input/output channels of the parallel test system. CONSTITUTION: A parallel test system(30) includes a plurality of input/output pins to test a plurality of DUTs(32,34). The parallel system includes a test device and a plurality of switching portions(38a,38b). The test device includes a test board having input/output channels(36a,36b) connected in parallel to corresponding information input/output pins of the DUTs. The switching portions are used for connecting selectively the information input/output pins of the DUTs to the input/output channels. A test process is sequentially or simultaneously performed according to the selection of the switching portions for the information input/output pins.

Abstract translation: 目的：通过使用并行测试系统的有限数量的输入/输出通道，提供DUT（待测器件）的并行测试系统，以增加并行测试过程中DUT的数量。 构成：并行测试系统（30）包括多个输入/输出引脚以测试多个DUT（32,34）。 并联系统包括测试装置和多个切换部分（38a，38b）。 测试装置包括具有与被测设备的相应信息输入/输出引脚并联连接的输入/输出通道（36a，36b）的测试板。 开关部分用于将DUT的信息输入/输出引脚选择性地连接到输入/输出通道。 根据用于信息输入/输出引脚的切换部分的选择，顺序地或同时地执行测试处理。

公开(公告)号：KR100351052B1

公开(公告)日：2002-09-05

申请号：KR1020000016464

申请日：2000-03-30

Applicant: 삼성전자주식회사

Inventor： 강성구 ,  민병준 ,  채효근 ,  방정호

IPC: H01L21/50

Abstract: 번인 공정에 있어서, 검사용 소켓을 반도체 패키지의 크기와 상관없이 공용으로 사용케 하는 반도체 패키지 가공용 로더에 관해 개시한다. 이를 위하여 본 발명은 반도체 패키지를 검사용 소켓에 정렬시키는 수단을 로더 내부에 형성함으로써 검사용 소켓에 사용된 어뎁터 기능을 대신한다. 따라서 검사용 소켓에서 어뎁터를 제거함으로써 검사용 소켓을 유니버셜 형태(universal type)로 만들 수 있다. 그러므로 검사용 소켓의 제작 비용을 줄이고, 관리에 소요되는 노력을 줄일 수 있다.

公开(公告)号：KR100348102B1

公开(公告)日：2002-08-09

申请号：KR1020010002569

申请日：2001-01-17

Applicant: 삼성전자주식회사

Inventor： 임성묵 ,  국중길 ,  채효근 ,  방정호

IPC: G01N21/88

CPC classification number: G06K5/00

Abstract: 본발명은광학적문자인식을통하여문자열끼리직접비교하는반도체제품의마킹결함검사방법을제공한다. 본발명에따른마킹결함검사방법은조립이완료된반도체제품의표면에마킹을실시한후 이루어지며, (a) 마킹문자를입력장치에서문자열로입력하는단계와, (b) 입력한문자열을저장장치에검사기준값으로저장하는단계와, (c) 반도체제품의마킹문자를판독장치에서문자이미지로판독하는단계와, (d) 판독한문자이미지를광학적문자인식장치에서문자열로인식하고문자열자료를얻는단계와, (e) 문자열자료를연산처리장치에서검사기준값문자열과비교하여마킹의양/불량을판정하는단계를포함한다. (a) 단계의입력장치는마킹문자를직접입력하는키보드이거나, 바코드로기록된마킹문자를읽어입력하는스캐너인것이바람직하며, 마킹문자는로트카드에기록된문자열또는바코드이다. 또한, (c) 단계의판독장치는전하결합소자와같은카메라또는스캐너가사용될수 있다.

公开(公告)号：KR100340715B1

公开(公告)日：2002-06-20

申请号：KR1019990046322

申请日：1999-10-25

Applicant: 삼성전자주식회사

Inventor： 오세장 ,  강기상 ,  방정호

IPC: G01R31/3183 ,  G01R31/26 ,  H01L21/66

CPC classification number: G01R31/31707 ,  G01R31/3183 ,  G01R31/318371

Abstract: 개선된테스트능력을가지는반도체테스트장치가개시된다. 그러한반도체테스트장치는, 노말용및 고속용포맷터를내부에포함하는테스터메인프레임; 및상기반도체디바이스로테스트에필요한신호들을인가하기위해제1주파수에서동작하는노말핀 드라이버들과, 상기장치의테스트능력을개선하기위하여상기반도체디바이스를보다고속으로동작시키는데 필요한신호들을상기반도체디바이스에인가하기위해상기제1주파수보다높은제2주파수에서동작하는고속핀 드라이버들을가지며, 상기테스터메인프레임과연결된테스트헤드를구비함에의해, 테스트능력이개선되고장비가격의상승요인이최소화된다.

公开(公告)号：KR1020010095435A

公开(公告)日：2001-11-07

申请号：KR1020000016464

申请日：2000-03-30

Applicant: 삼성전자주식회사

Inventor： 강성구 ,  민병준 ,  채효근 ,  방정호

IPC: H01L21/50

CPC classification number: G01R31/2867 ,  G01R1/0408 ,  H01L2224/75 ,  H01L2224/81

Abstract: PURPOSE: A loader for processing a semiconductor package with a package guide and a method for using the same are provided to apply a test socket to semiconductor packages of different sizes by using a package guide. CONSTITUTION: A loader body(102) is moved by an external signal. A nozzle body(112) including a vacuum line is formed at a lower end of loader body(102). The nozzle body(112) performs a vertical movement by the external signal. A vacuum absorption head(114) is formed at a lower end of the nozzle body(112). The vacuum absorption head(114) is connected with the vacuum line in order to load or unload a semiconductor package(116). A socket cover push head(118) is used for pushing a socket cover of a test socket. A package guide(104,106,108,110) is formed at the inside of the socket cover push head and the outside of the nozzle body(102) and the vacuum absorption head(114). The package guide(104,106,108,110) is opened or shut according to a loading state or a unloading state of the semiconductor package(116).

Abstract translation: 目的：提供一种用于处理具有封装引导件的半导体封装的加载器及其使用方法，以通过使用封装引导件将测试插座施加到不同尺寸的半导体封装。 构成：装载机主体（102）由外部信号移动。 在装载机主体（102）的下端形成包括真空管线的喷嘴体（112）。 喷嘴体（112）通过外部信号进行垂直移动。 在喷嘴体（112）的下端形成真空吸收头（114）。 真空吸收头（114）与真空管线连接，以便加载或卸载半导体封装（116）。 插座盖推头（118）用于推动测试插座的插座盖。 包装引导件（104,106,108,110）形成在插座盖推动头的内部和喷嘴体（102）和真空吸收头（114）的外部。 封装引导件（104,106,108,110）根据半导体封装（116）的装载状态或卸载状态而被打开或关闭。