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公开(公告)号:KR1020030009656A
公开(公告)日:2003-02-05
申请号:KR1020010044205
申请日:2001-07-23
Applicant: 삼성전자주식회사
IPC: H01L21/68
Abstract: PURPOSE: A method for inspecting storage states of semiconductor chips stored within a tray is provided to detect correctly the storage states of the semiconductor chips by inspecting accurately marks of the semiconductor chips stored within the tray. CONSTITUTION: A tray including semiconductor chips is prepared. The first image for displaying one region of the semiconductor chips is obtained(710). A reference point is set up by separating an outline of the semiconductor chip from the first image(720). A search region is set up as a predetermined region between the reference point and the semiconductor chip region(730). The second image is obtained by using another lighting condition(740). The mark of the semiconductor chip is checked within the search region of the second image(750). A storage state of the semiconductor is determined according to the presence of the mark(760). A position of the semiconductor is corrected according to the storage state of the semiconductor(770). An inspection process is finished(780).
Abstract translation: 目的:提供一种用于检查存储在托盘内的半导体芯片的存储状态的方法,以通过检查存储在托盘内的半导体芯片的精确标记来正确地检测半导体芯片的存储状态。 构成:制备包含半导体芯片的托盘。 获得用于显示半导体芯片的一个区域的第一图像(710)。 通过将半导体芯片的轮廓与第一图像(720)分离来建立参考点。 搜索区域被设置为参考点和半导体芯片区域之间的预定区域(730)。 通过使用另一照明条件(740)获得第二图像。 在第二图像的搜索区域内检查半导体芯片的标记(750)。 根据标记的存在来确定半导体的存储状态(760)。 根据半导体的存储状态来校正半导体的位置(770)。 检查过程结束(780)。
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公开(公告)号:KR1020020025303A
公开(公告)日:2002-04-04
申请号:KR1020000056986
申请日:2000-09-28
Applicant: 삼성전자주식회사
IPC: H01L21/66
Abstract: PURPOSE: A method for fabricating a semiconductor device using a functional test for wafer level is provided to reduce a time for test and a cost for test by unifying a test process for a semiconductor device. CONSTITUTION: A multitude of semiconductor chip is provided on a surface of a wafer(110). A functional test for the semiconductor chips is performed in a wafer level(120). The wafer is divided into a multitude of semiconductor chip by sawing the wafer according to a predetermined size(140). A packaging process for the semiconductor chips is performed(150). An electric test(112,152) such as a DC test can be performed after the packaging process is finished. The completed semiconductor devices are stored in a storehouse(160). A laser repair process for bad semiconductor chips can be performed and the functional test can be performed again after the functional test is performed(124).
Abstract translation: 目的:提供一种使用晶片级的功能测试制造半导体器件的方法,以通过统一半导体器件的测试过程来减少测试时间和测试成本。 构成:在晶片(110)的表面上设置多个半导体芯片。 在晶片级(120)中执行半导体芯片的功能测试。 通过根据预定尺寸锯切晶片将晶片分成多个半导体芯片(140)。 执行半导体芯片的封装处理(150)。 在包装过程结束后,可以进行DC测试等电气测试(112,152)。 完成的半导体器件存储在仓库(160)中。 可以进行用于坏的半导体芯片的激光修复处理,并且可以在执行功能测试之后再次执行功能测试(124)。
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公开(公告)号:KR1020010028962A
公开(公告)日:2001-04-06
申请号:KR1019990041518
申请日:1999-09-28
Applicant: 삼성전자주식회사
IPC: H01L21/68
Abstract: PURPOSE: A tray for a chip scale package(CSP) is provided to prevent the CSP from being damaged by fluctuation generated in transferring the tray, by making the CSP contained in a pocket part made of a soft buffer material. CONSTITUTION: A base tray(40) is of a plate shape. A pocket part(20) is fixedly coupled to a surface of the base tray, and has a plurality of pockets(22) which are dented inward regarding a surface to contain a chip scale package(CSP)(30). The pocket part is made of a buffer material to absorb impact caused by fluctuation of the CSP contained in the pocket.
Abstract translation: 目的:提供一种用于芯片级封装(CSP)的托盘,用于防止CSP在传送托盘时产生的波动受到损坏,方法是使CSP包含在由软缓冲材料制成的口袋部件中。 构成:底盘(40)为板状。 口袋部分(20)固定地联接到基盘的表面,并且具有多个凹口(22),其相对于表面向内凹陷以容纳芯片级封装(CSP)(30)。 口袋部分由缓冲材料制成,以吸收由包含在口袋中的CSP波动引起的冲击。
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公开(公告)号:KR100351052B1
公开(公告)日:2002-09-05
申请号:KR1020000016464
申请日:2000-03-30
Applicant: 삼성전자주식회사
IPC: H01L21/50
Abstract: 번인 공정에 있어서, 검사용 소켓을 반도체 패키지의 크기와 상관없이 공용으로 사용케 하는 반도체 패키지 가공용 로더에 관해 개시한다. 이를 위하여 본 발명은 반도체 패키지를 검사용 소켓에 정렬시키는 수단을 로더 내부에 형성함으로써 검사용 소켓에 사용된 어뎁터 기능을 대신한다. 따라서 검사용 소켓에서 어뎁터를 제거함으로써 검사용 소켓을 유니버셜 형태(universal type)로 만들 수 있다. 그러므로 검사용 소켓의 제작 비용을 줄이고, 관리에 소요되는 노력을 줄일 수 있다.
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公开(公告)号:KR100348102B1
公开(公告)日:2002-08-09
申请号:KR1020010002569
申请日:2001-01-17
Applicant: 삼성전자주식회사
IPC: G01N21/88
CPC classification number: G06K5/00
Abstract: 본발명은광학적문자인식을통하여문자열끼리직접비교하는반도체제품의마킹결함검사방법을제공한다. 본발명에따른마킹결함검사방법은조립이완료된반도체제품의표면에마킹을실시한후 이루어지며, (a) 마킹문자를입력장치에서문자열로입력하는단계와, (b) 입력한문자열을저장장치에검사기준값으로저장하는단계와, (c) 반도체제품의마킹문자를판독장치에서문자이미지로판독하는단계와, (d) 판독한문자이미지를광학적문자인식장치에서문자열로인식하고문자열자료를얻는단계와, (e) 문자열자료를연산처리장치에서검사기준값문자열과비교하여마킹의양/불량을판정하는단계를포함한다. (a) 단계의입력장치는마킹문자를직접입력하는키보드이거나, 바코드로기록된마킹문자를읽어입력하는스캐너인것이바람직하며, 마킹문자는로트카드에기록된문자열또는바코드이다. 또한, (c) 단계의판독장치는전하결합소자와같은카메라또는스캐너가사용될수 있다.
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公开(公告)号:KR1020010095435A
公开(公告)日:2001-11-07
申请号:KR1020000016464
申请日:2000-03-30
Applicant: 삼성전자주식회사
IPC: H01L21/50
CPC classification number: G01R31/2867 , G01R1/0408 , H01L2224/75 , H01L2224/81
Abstract: PURPOSE: A loader for processing a semiconductor package with a package guide and a method for using the same are provided to apply a test socket to semiconductor packages of different sizes by using a package guide. CONSTITUTION: A loader body(102) is moved by an external signal. A nozzle body(112) including a vacuum line is formed at a lower end of loader body(102). The nozzle body(112) performs a vertical movement by the external signal. A vacuum absorption head(114) is formed at a lower end of the nozzle body(112). The vacuum absorption head(114) is connected with the vacuum line in order to load or unload a semiconductor package(116). A socket cover push head(118) is used for pushing a socket cover of a test socket. A package guide(104,106,108,110) is formed at the inside of the socket cover push head and the outside of the nozzle body(102) and the vacuum absorption head(114). The package guide(104,106,108,110) is opened or shut according to a loading state or a unloading state of the semiconductor package(116).
Abstract translation: 目的:提供一种用于处理具有封装引导件的半导体封装的加载器及其使用方法,以通过使用封装引导件将测试插座施加到不同尺寸的半导体封装。 构成:装载机主体(102)由外部信号移动。 在装载机主体(102)的下端形成包括真空管线的喷嘴体(112)。 喷嘴体(112)通过外部信号进行垂直移动。 在喷嘴体(112)的下端形成真空吸收头(114)。 真空吸收头(114)与真空管线连接,以便加载或卸载半导体封装(116)。 插座盖推头(118)用于推动测试插座的插座盖。 包装引导件(104,106,108,110)形成在插座盖推动头的内部和喷嘴体(102)和真空吸收头(114)的外部。 封装引导件(104,106,108,110)根据半导体封装(116)的装载状态或卸载状态而被打开或关闭。
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公开(公告)号:KR100236302B1
公开(公告)日:1999-12-15
申请号:KR1019960069101
申请日:1996-12-20
Applicant: 삼성전자주식회사
IPC: H01L23/12
Abstract: 본 발명은, 반도체 칩 패키지 검사용 소켓에 관한 것으로, 소켓에 삽입된 반도체 칩 패키지의 리드와 전기적 접속되는 소켓 리드의 리드 접속부가 소켓에 삽입된 반도체 칩 패키지의 리드를 중심으로 상부와 하부에 각기 적어도 1개 이상 형성되어 있으며, 그 리드 접속부가 탄성부의 복원력에 의해 리드의 상부면과 하부면을 동시에 찍어 접속함으로써, 리드와 소켓 리드 사이의 접속 신뢰성이 향상되는 장점이 있다.
그리고, 소켓 리드 1개당 여러 개의 리드 접속부를 갖기 때문에 어느 하나의 리드 접속부가 망실되더라도 소켓의 사용이 가능하기 때문에 소켓의 수명이 연장되는 장점이 있다.-
公开(公告)号:KR1020030036976A
公开(公告)日:2003-05-12
申请号:KR1020010067930
申请日:2001-11-01
Applicant: 삼성전자주식회사
IPC: H01L21/60
Abstract: PURPOSE: A device for detecting appearance of solder balls for bga package and method for setting optimum lighting condition thereof are provided to increase reliability of inspecting equipment by detecting whether a lighting condition is suitable even if time passes or inspection surroundings vary before an inspection is performed on a real object. CONSTITUTION: A reference sample is transferred from a reference sample storing unit to an inspecting unit according to a start signal of inspection. The reference sample is measured in the inspecting unit according to an arbitrary lighting condition. A difference(measurement error) between the measurement value of the reference sample and a known real value of the reference sample is calculated. The measurement error is compared with an allowable error to obtain an optimum condition regarding the brightness of lighting.
Abstract translation: 目的:提供一种用于检测用于bga封装的焊球外观的装置及其最佳照明条件的设定方法,以提高检查设备的可靠性,即使在进行检查之前检测照明条件是否合适,即使时间过去或检查环境变化 在一个真正的对象。 规定:参考样品根据检查的起始信号从参考样品存储单元传送到检查单元。 根据任意的照明条件,在检查单元中测量基准样品。 计算参考样本的测量值和参考样本的已知实际值之间的差异(测量误差)。 将测量误差与允许误差进行比较,以获得关于照明亮度的最佳条件。
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公开(公告)号:KR1020020085714A
公开(公告)日:2002-11-16
申请号:KR1020010025411
申请日:2001-05-10
Applicant: 삼성전자주식회사
IPC: H05K3/34
CPC classification number: H05K1/0269 , G06T7/0004 , H05K3/3436
Abstract: PURPOSE: A method for examining a shape of solder ball is provided to search previously a damage of a product generated from a process for examining an electrical characteristic for the product such as a BGA(Ball Grid Array) package by detecting a flake of a solder ball. CONSTITUTION: The first image of solder balls is generated by using a CCD(Charge Coupled Device) camera(180). An analyzer determines center coordinates of each solder ball by using the first image(182). Information about normal region of the solder balls is obtained by using diameters of each solder ball(184). The remaining region except for the normal region is set up as a test region(186). The second image of solder balls is generated by using the CCD camera(188). The first image is compared to the second image(190). A solder ball test process is performed by investigating and detecting flakes of the solder balls(192).
Abstract translation: 目的:提供一种用于检查焊球形状的方法,用于通过检测焊料的片状物来检测由用于检查诸如BGA(球栅阵列)封装的产品的电特性的处理产生的产品的损坏 球。 构成:使用CCD(电荷耦合器件)相机(180)产生第一个焊球图像。 分析仪通过使用第一图像(182)来确定每个焊球的中心坐标。 通过使用每个焊球(184)的直径获得关于焊球正常区域的信息。 除了正常区域之外的剩余区域被设置为测试区域(186)。 通过使用CCD照相机(188)产生焊球的第二图像。 将第一图像与第二图像进行比较(190)。 通过研究和检测焊球(192)的薄片来进行焊球测试过程。
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公开(公告)号:KR100331546B1
公开(公告)日:2002-04-06
申请号:KR1019990015206
申请日:1999-04-28
Applicant: 삼성전자주식회사
IPC: H01L23/32
CPC classification number: G01R1/0466
Abstract: 반도체패키지를전기적으로검사할때 접촉불량으로발생하는오픈/쇼트(open/short) 결함을억제하고, 제조비용을절감할수 있는반도체패키지검사공정에사용되는소켓핀및 이를이용한소켓에관해개시한다. 이를위하여본 발명은반도체패키지(package) 리드(lead)와접촉되는소켓핀(socket pin) 상부와, 상기소켓핀상부와연결되며상기소켓핀상부가반도체패키지리드에의해아래로눌러지는힘을두 지점에서완충시킬수 있는소켓핀몸체와, 상기소켓핀몸체와연결되며상기소켓핀상부및 소켓핀몸체에서발생되는탄성을지지할수 있는소켓핀하부와, 상기소켓핀하부와연결되며전기적인신호를외부로전달하거나받아들이는통로역할을하는소켓하부핀을구비하는것을특징으로하는소켓핀및 이러한소켓핀을구비하는소켓을제공한다.
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