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公开(公告)号：KR101866486B1
公开(公告)日：2018-06-12
申请号：KR1020110007237
申请日：2011-01-25
Applicant: 에스케이하이닉스 주식회사 , 연세대학교 산학협력단
IPC: G05F1/567
CPC classification number: G01K7/346
Abstract: 본발명에따른온도감지회로는, 지연라인을포함하며, 상기지연라인의지연값에대응되는펄스폭을가진소스신호를생성하는신호생성부; 상기소스신호의펄스폭을확장하여비교신호를생성하는펄스폭확장부; 및상기비교신호와기준신호의펄스폭차이를이용하여온도변화를감지하는변화감지부를포함한다.
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公开(公告)号：KR101477052B1
公开(公告)日：2014-12-31
申请号：KR1020140041312
申请日：2014-04-07
Applicant: 연세대학교 산학협력단
CPC classification number: H03K3/354 , H03K3/011 , H03K3/0315
Abstract: The present invention relates to a ring oscillator, a process variation sensing apparatus, and a semiconductor chip including the same. According to an embodiment of the present invention, the ring oscillator includes an inverter of a single transistor type which includes a pull-up transistor and a pull-down transistor consisting of a PMOS or an NMOS.
Abstract translation: 本发明涉及环形振荡器，工艺变化检测装置和包括该振荡器的半导体芯片。 根据本发明的实施例，环形振荡器包括单晶体管类型的反相器，其包括上拉晶体管和由PMOS或NMOS组成的下拉晶体管。
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公开(公告)号：KR1020130030838A
公开(公告)日：2013-03-28
申请号：KR1020110094365
申请日：2011-09-20
Applicant: 연세대학교 산학협력단
IPC: G01R31/28
Abstract: PURPOSE: A signal generator and an automatic test apparatus are provided to improve accuracy of an automatic test. CONSTITUTION: A signal generator(100) includes an integer delay generator, an edge vernier and an offset compensation unit(130). The offset compensation unit receives a reference signal, an operation control signal of the edge vernier and the integer delay generator, and a processing signal of the edge vernier and generates an output signal having an output signal delaying the reference signal with a specific space. The offset compensation unit includes a time-digital conversion unit(131), a comparison unit(132) and a control unit(133). The time-digital conversion unit converts phase difference between the reference signal and the operation control signal into a digital value. The comparison unit generates an output signal by comparing the digital value with the predetermined value. [Reference numerals] (131) Time-digital conversion unit; (132) Comparison unit; (133) Control unit
Abstract translation: 目的：提供信号发生器和自动测试装置，以提高自动测试的精度。 构成：信号发生器（100）包括整数延迟发生器，边缘游标和偏移补偿单元（130）。 偏移补偿单元接收参考信号，边缘游标和整数延迟发生器的操作控制信号，以及边缘游标的处理信号，并产生输出信号，该输出信号具有延迟参考信号的特定空间。 偏移补偿单元包括时间 - 数字转换单元（131），比较单元（132）和控制单元（133）。 时间数字转换单元将参考信号和操作控制信号之间的相位差转换为数字值。 比较单元通过将数字值与预定值进行比较来产生输出信号。 （参考编号）（131）时间数字转换单元; （132）比较单位; （133）控制单元
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公开(公告)号：KR1020120090618A
公开(公告)日：2012-08-17
申请号：KR1020110011142
申请日：2011-02-08
Applicant: 연세대학교 산학협력단
CPC classification number: H03K3/017
Abstract: PURPOSE: An edge combiner and a frequency multiplier and a frequency multiplying method using the edge combiner are provided to be operated at high speed by controlling a turn-off operation of a PMOS transistor in a differential cascode voltage switch logic through a separate control unit. CONSTITUTION: A first signal output part(510) includes a first control part and a second control part which respectively control turn-off operations of a first PMOS(P-channel Metal Oxide Semiconductor) transistor and a second PMOS transistor in a differential cascode voltage switch logic. A second signal output part(520) controls a duty ratio of signals by toggling each output signal of the first signal output part. The first control part comprises a first inverter, a first NMOS(N-channel Metal Oxide Semiconductor) passgate, and a first shut off PMOS transistor. Drain terminals of the first shut off PMOS transistor and the first NMOS passgate are connected to the first PMOS transistor. The second controller comprises a second inverter, a second NMOS passgate, and a second shut off PMOS transistor.
Abstract translation: 目的：通过分离控制单元控制差分共源共栅电压开关逻辑中的PMOS晶体管的关断操作，提供边缘组合器和使用边缘组合器的倍频方法以高速工作。 构成：第一信号输出部分（510）包括第一控制部分和第二控制部分，其分别控制差分共源共栅电压中的第一PMOS（P沟道金属氧化物半导体）晶体管和第二PMOS晶体管的截止操作 开关逻辑。 第二信号输出部分（520）通过切换第一信号输出部分的每个输出信号来控制信号的占空比。 第一控制部分包括第一反相器，第一NMOS（N沟道金属氧化物半导体）通路和第一截止PMOS晶体管。 第一截止PMOS晶体管和第一NMOS通道的漏极端子连接到第一PMOS晶体管。 第二控制器包括第二反相器，第二NMOS通道和第二截止PMOS晶体管。
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公开(公告)号：KR1020120090561A
公开(公告)日：2012-08-17
申请号：KR1020110011049
申请日：2011-02-08
Applicant: 연세대학교 산학협력단
IPC: H03L7/081 , G01R31/3183 , G01R31/26 , H01L21/66
CPC classification number: H03L7/0814 , G01R31/26 , G01R31/3183 , H03K5/135
Abstract: PURPOSE: A phase delay signal generator, equipment for a chip test including the same, and a method for creating a phase delay signal are provided to prevent the generation of mismatch and to eliminate PVT variation in a linear delay cell. CONSTITUTION: A phase delay signal generator comprises a digital control vibrator(100), a controller(200), a plurality of single phase generators(300), and a multiplexor(400). The digital control vibrator creates a reference signal. The controller controls the digital control vibrator. The plurality of single phase generators locks an input signal inputted from a fixed number delay generator to a reference signal created by the digital control vibrator and creates a plurality of single phase delay signals. The multiplexor selects a special signal among the plurality of single phase delay signals and transfers the special signal to a linear phase delay cell.
Abstract translation: 目的：提供相位延迟信号发生器，用于包括该相位延迟信号的芯片测试的设备和用于产生相位延迟信号的方法，以防止失配的产生并消除线性延迟单元中的PVT变化。 构成：相位延迟信号发生器包括数字控制振动器（100），控制器（200），多个单相发生器（300）和多路复用器（400）。 数字控制振动器产生参考信号。 控制器控制数字控制振动器。 多个单相发生器将从固定数量延迟发生器输入的输入信号锁定到由数字控制振动器产生的参考信号，并产生多个单相延迟信号。 多路复用器在多个单相延迟信号中选择特殊信号，并将特殊信号传送到线性相位延迟单元。
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Patent Agency Ranking
公开(公告)号：KR101165730B1
公开(公告)日：2012-07-18
申请号：KR1020090135163
申请日：2009-12-31
Applicant: 연세대학교 산학협력단
IPC: H03K3/037 , H03K3/3562
Abstract: 본 발명은 슬립 모드(Sleep Mode) 이전 상태의 데이터를 저장하는 기능을 가지는 데이터 리텐션 회로에 관한 것이다. 본 발명의 실시 예에 따른 데이터 리텐션 회로는 제 1 노드 및 제 2 노드에 연결되는 마스터 래치, 제 3 노드 및 제 4 노드에 연결되는 슬래이브 래치, 상기 제 2 노드의 전압이 하이(high)인 경우에 상기 제 1 노드와 상기 제3 노드 사이에 전류 통로를 형성하는 제 1 스위치 및 상기 제 1 노드의 전압이 하이인 경우에 상기 제 2 노드와 상기 제 4 노드 사이에 전류 통로를 형성하는 제 2 스위치를 포함한다.
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公开(公告)号：KR101027760B1
公开(公告)日：2011-04-07
申请号：KR1020090135162
申请日：2009-12-31
Applicant: 연세대학교 산학협력단
IPC: G11C8/00 , G11C11/407 , G11C7/22 , G11C7/10
CPC classification number: G11C7/222 , G11C7/1066 , G11C11/4076 , H03K5/1565 , H03L7/0812 , H03L7/089
Abstract: PURPOSE: A clock generating device for a delayed locked loop and a clock generating method thereof are provided to have a combination unit for outputting an output clock signal, thereby being implemented in a narrow area. CONSTITUTION: In a clock generating device for a delayed locked loop and a clock generating method thereof, a first delay line(131) generates a first delay clock signal. A second delay line(133) generates a second delay clock signal. A third delay line(135) generates a third delay clock signal. A fourth delay line(137) generates a fourth delay clock signal. A first clock combination unit(132) combines the first delay clock signal and the third delay clock signal. The first clock combination unit generates a first output clock signal. The second clock combination unit(134) combines the second delay clock signal and a fourth delay clock signal. The second clock combination unit generates the second output clock signal. A third clock combination unit(136) combines the third delay clock signal and the first delay clock signal. The third clock combination unit generates the third output clock signal. A fourth clock combination unit(138) combines the fourth delay clock signal with the second delay clock signal. The fourth clock combination unit generates the fourth output clock signal.
Abstract translation: 目的：提供一种用于延迟锁定环的时钟产生装置及其时钟产生方法，以具有用于输出输出时钟信号的组合单元，从而在狭窄的区域中实现。 构成：在用于延迟锁定环的时钟产生装置及其时钟产生方法中，第一延迟线（131）产生第一延迟时钟信号。 第二延迟线（133）产生第二延迟时钟信号。 第三延迟线（135）产生第三延迟时钟信号。 第四延迟线（137）生成第四延迟时钟信号。 第一时钟组合单元（132）组合第一延迟时钟信号和第三延迟时钟信号。 第一时钟组合单元产生第一输出时钟信号。 第二时钟组合单元（134）组合第二延迟时钟信号和第四延迟时钟信号。 第二时钟组合单元产生第二输出时钟信号。 第三时钟组合单元（136）组合第三延迟时钟信号和第一延迟时钟信号。 第三时钟组合单元产生第三输出时钟信号。 第四时钟组合单元（138）将第四延迟时钟信号与第二延迟时钟信号组合。 第四时钟组合单元产生第四输出时钟信号。
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公开(公告)号：KR102001691B1
公开(公告)日：2019-07-18
申请号：KR1020140029623
申请日：2014-03-13
Applicant: 에스케이하이닉스 주식회사 , 연세대학교 산학협력단
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公开(公告)号：KR1020180093580A
公开(公告)日：2018-08-22
申请号：KR1020170019866
申请日：2017-02-14
Applicant: 연세대학교 산학협력단
IPC: G01R19/175 , H02M3/158 , H02M3/155
CPC classification number: Y02B70/1491 , G01R19/175 , H02M3/1582 , H02M2003/1552
Abstract: 일실시예에따른일 실시예에따른오프셋제어에의한제로전류감지센서는부스트컨버터를구성하는반도체의스위치노드전압값과부하노드의전압값을비교하여, 상기스위치의온/오프동작시간을오프셋으로제어하는제어부및 상기오프셋으로상기스위치의온/오프동작을구동하는구동회로를포함한다.
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公开(公告)号：KR101798324B1
公开(公告)日：2017-11-15
申请号：KR1020160032952
申请日：2016-03-18
Applicant: 연세대학교 산학협력단
Abstract: 일실시예에따른에너지하베스팅용직류-직류변환장치는연결부하로흐르는전류값에기초하여헤비(heavy) 모드또는라이트(light) 모드를결정하는결정부, 상기결정된모드에기초하여, 열전소자어레이의구성을직렬또는병렬로재구성하는어레이재구성부, 상기결정된모드에기초하여, 변환부의스위칭주파수를제어하는주파수제어부및 상기제어된스위칭주파수에기초하여, 상기재구성된열전소자어레이에서생성된직류전압을상기부하에필요한전압으로변환하는변환부를포함한다.
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