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公开(公告)号：KR101092699B1
公开(公告)日：2011-12-09
申请号：KR1020100042733
申请日：2010-05-07
Applicant: 서울대학교산학협력단
IPC: H03K19/0948 , H03F3/70 , H03F3/45
CPC classification number: H03F3/70 , H03F3/45179 , H03F2203/45512
Abstract: 본발명은캐스코드연결된한 쌍의 PMOS 트랜지스터의각각의게이트사이와, 캐스코드연결된한 쌍의 NMOS 트랜지스터의각각의게이트사이에부트스트랩캐패시터를설치하고, 데이터샘플링단계(Φ)에서는전류기근을통해 PMOS 트랜지스터와 NMOS 트랜지스터를모두약반전동작시켜부트스트랩캐패시터에입력전압(V)과기준전압(V, V) 사이의전위차에대응된전하를저장하였다가, 전하전달단계(Φ)에서는입력전압이극성에따라 NMOS 트랜지스터쌍 또는 PMOS 트랜지스터쌍 중어느한 쌍을강반전으로구동하고다른한 쌍은컷오프동작하도록하여넓은대역폭을확보하도록하고, 전하전달후 정상상태단계(Φ)에서는 PMOS 트랜지스터와 NMOS 트랜지스터를모두약반전회귀시켜높은이득과함께전력소모를방지하는방식을제공한다.
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公开(公告)号：KR1020110132043A
公开(公告)日：2011-12-07
申请号：KR1020100051836
申请日：2010-06-01
Applicant: 서울대학교산학협력단
IPC: G02F1/1337
CPC classification number: G02F1/133753 , G02F2201/501
Abstract: PURPOSE: A liquid crystal display device, a manufacturing method thereof, and a method for manufacturing a liquid crystal aligned substrate are provided to obtain a wide viewing angle by implementing multi-domain using a protection layer with fluorine polymer. CONSTITUTION: A second substrate(2) faces a first substrate(1). A first vertically aligned layer(10) is located on the first substrate and includes a first region with a first alignment direction and a second region with a second alignment direction. A second vertically aligned layer(20) is located on the second substrate and includes a third region with a third alignment direction and a fourth region with a fourth alignment direction.
Abstract translation: 目的：提供一种液晶显示装置及其制造方法以及液晶取向基板的制造方法，通过利用氟聚合物保护层实现多域来获得宽视角。 构成：第二衬底（2）面向第一衬底（1）。 第一垂直取向层（10）位于第一基板上，并且包括具有第一取向方向的第一区域和具有第二取向方向的第二区域。 第二垂直取向层（20）位于第二基板上，并且包括具有第三取向方向的第三区域和具有第四取向方向的第四区域。
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公开(公告)号：KR1020100088653A
公开(公告)日：2010-08-10
申请号：KR1020097023582
申请日：2009-01-22
Applicant: (주)글로넷시스템즈 , 서울대학교산학협력단
CPC classification number: H03L7/0995 , H03L7/0807 , H04L7/0079 , H04L7/033 , H04L7/0331
Abstract: PURPOSE: All-digital clock data recovery device and a transceiver implemented thereof are provided to digitalize the whole of a clock data restoring unit by implementing a charge pump circuit and a voltage controlled generator with a digital circuit. CONSTITUTION: A phase detector(10) samples serial data. A phase detector outputs the digital signal sequence of data and edge. A deserializer changes the digital signal sequence into a bus signal. A digital controlled oscillator(200) is comprised of a multi-stage inverter chain. The digital controlled oscillator comprises a variable resistance switching matrix the digital controlled oscillator generates a clock having an adjusted oscillation frequency. The digital controlled oscillator provides a clock to the phase detector.
Abstract translation: 目的：提供全数字时钟数据恢复装置及其实现的收发器，通过实现电荷泵电路和具有数字电路的电压控制发生器来数字化整个时钟数据恢复单元。 构成：相位检测器（10）对串行数据进行采样。 相位检测器输出数字信号的数据和边沿。 解串器将数字信号序列改变为总线信号。 数字控制振荡器（200）由多级反相器链组成。 数字控制振荡器包括可变电阻开关矩阵，数字控制振荡器产生具有调整的振荡频率的时钟。 数字控制振荡器为相位检测器提供时钟。
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公开(公告)号：KR1020100071888A
公开(公告)日：2010-06-29
申请号：KR1020090076788
申请日：2009-08-19
Applicant: 삼성전자주식회사 , 서울대학교산학협력단
Abstract: PURPOSE: A variable capacitor, a digitally controlled oscillator, and a digital phase locked loop are provided to minimize the size of capacitance by connection a plurality of capacitor groups in parallel. CONSTITUTION: A capacitor unit(110) includes a plurality of capacitor groups which are arranged in a matrix shape. Based on line/ row selection signal with respect to the matrix, a switch unit(120) connects the capacitor groups in parallel and adjusts capacitance. A first capacitor sub-group has a first capacitance. A second capacitor sub-group has other capacitance which is different from the first capacitance. An adjust unit(130) selects the capacitor groups based on the size of the capacitances.
Abstract translation: 目的：提供可变电容器，数字控制振荡器和数字锁相环，以通过并联连接多个电容器组来最小化电容的尺寸。 构成：电容器单元（110）包括以矩阵形状排列的多个电容器组。 基于相对于矩阵的线/行选择信号，开关单元（120）并联连接电容器组并调整电容。 第一电容器子组具有第一电容。 第二电容器子组具有与第一电容不同的其它电容。 调整单元（130）基于电容的大小来选择电容器组。
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Patent Agency Ranking
公开(公告)号：KR101632657B1
公开(公告)日：2016-06-23
申请号：KR1020090076780
申请日：2009-08-19
Applicant: 삼성전자주식회사 , 서울대학교산학협력단
Abstract: 타임투디지털컨버터가개시된다. 본타임투디지털컨버터는, 제1 신호및 제2 신호를수신하며, 직렬연결된복수의지연소자를이용하여제2 신호를단계적으로지연시키고, 지연된제2 신호와제1 신호를비교하여제1 신호에대한제2 신호의위상에러를출력하는컨버터, 제1 신호및 복수의지연소자의노드중 하나의노드로부터제3 신호를수신하며, 제1 신호및 제3 신호에대한위상차를출력하는위상주파수검출기, 및, 주파수검출기의출력신호와제2 신호를이용하여, 제1 신호대한제2 신호의주파수에러를디지털코드로출력하는주파수검출기를포함한다. 이에따라, 본타임투디지털컨버터는입력되는두 신호간의위상차이뿐만아니라주파수차이까지검출할수 있다.
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公开(公告)号：KR1020140100673A
公开(公告)日：2014-08-18
申请号：KR1020130013653
申请日：2013-02-07
Applicant: 서울대학교산학협력단
IPC: H05B37/02
CPC classification number: H05B33/0827 , H05B33/083 , H02M3/1582 , H05B33/0812
Abstract: An apparatus for driving a light emitting device according to an embodiment of the present invention includes: a power supply part for supplying a DC current including a ripple with a constant period; and a light emitting device array. The light emitting device array includes a plurality of unit light emitting device arrays. Each unit light emitting device array includes a light emitting device string; a switch for supplying or blocking the DC current supplied to the light emitting device string from the power supply part; a capacitor for smoothing the DC current supplied by the power supply part; and a control part for controlling the switch to be switched on or off. The control part divides a period of the DC current into m sections where the number ″m″ is relatively prime to the number (n) of the unit light emitting device arrays, and controls the switch so that a DC current of each section is applied to the unit light emitting device arrays in sequence.
Abstract translation: 根据本发明实施例的用于驱动发光器件的装置包括：电源部分，用于提供包括恒定周期的纹波的DC电流; 和发光器件阵列。 发光器件阵列包括多个单位发光器件阵列。 每个单位发光器件阵列包括发光器件串; 用于从供电部分提供或阻挡提供给发光器件串的DC电流的开关; 用于平滑由电源部分提供的DC电流的电容器; 以及用于控制开关被打开或关闭的控制部分。 控制部将直流电流的周期分割为与单位发光元件阵列的数量（n）相对应的数量“m”的m个部分，并且控制开关，使得每个部分的直流电流被施加 依次连接到单元发光器件阵列。
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公开(公告)号：KR101278109B1
公开(公告)日：2013-06-24
申请号：KR1020120041062
申请日：2012-04-19
Applicant: 서울대학교산학협력단
CPC classification number: H03L7/07 , G04F10/005 , H03L7/0991 , H03L2207/50
Abstract: PURPOSE: A digital phase locked loop which has a low long term jitter is provided to reduce power consumption and the size. CONSTITUTION: A first phase locked loop(1) includes a first digital control oscillator(200) in which a frequency of an output signal is controlled according to a first digital control code(M). The first digital control oscillator includes a second phase locked loop(200'). The second phase locked loop receives the first digital control code, controls a dividing ratio about a signal on a feedback path according to the first digital control code, and exists inside of the first phase locked loop. A dividing block(600) divides the output signal of the second phase locked loop and automatically selects a dividing ratio by using a control signal which controls the oscillator of the second phase locked loop. [Reference numerals] (280) DOC block; (600) Dividing block
Abstract translation: 目的：提供具有低长期抖动的数字锁相环，以减少功耗和尺寸。 构成：第一锁相环（1）包括第一数字控制振荡器（200），其中根据第一数字控制码（M）控制输出信号的频率。 第一数字控制振荡器包括第二锁相环（200'）。 第二锁相环接收第一数字控制码，根据第一数字控制码控制反馈路径上的信号的分频比，并且存在于第一锁相环内。 分割块（600）划分第二锁相环的输出信号，并通过使用控制第二锁相环的振荡器的控制信号来自动选择分频比。 （附图标记）（280）DOC块; （600）分隔块
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公开(公告)号：KR1020160121111A
公开(公告)日：2016-10-19
申请号：KR1020150050625
申请日：2015-04-10
Applicant: 에스케이하이닉스 주식회사 , 서울대학교산학협력단
CPC classification number: H04L7/0079 , H03L7/0812 , H03L7/087 , H03L7/0891 , H03L7/0896 , H04L7/0008 , H04L7/0012 , H04L7/0037 , H04L7/02 , H04L7/0337 , H04L7/04
Abstract: 본기술에의한데이터수신장치는데이터스트로브신호에따라내부클록신호로부터샘플링클록신호를생성하는샘플링클록생성부; 및샘플링클록신호에따라데이터신호를샘플링하는샘플링부를포함한다.
Abstract translation: 数据接收机包括：采样时钟发生器，被配置为根据数据选通信号从内部时钟信号产生采样时钟信号;以及采样器，被配置为根据采样时钟信号对数据信号进行采样。
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公开(公告)号：KR101640495B1
公开(公告)日：2016-07-19
申请号：KR1020090076788
申请日：2009-08-19
Applicant: 삼성전자주식회사 , 서울대학교산학협력단
Abstract: 가변커패시터가개시된다. 본가변커패시터는, 매트릭스형태로배열되는복수의커패시터그룹을포함하는커패시터부, 및, 매트릭스에대한행 및열 선택신호에따라, 복수의커패시터그룹을병렬연결하여커패시턴스를조정하는스위치부를포함한다. 이에의해, 사이즈를소형화하면서커패시턴스변화율을높일수 있는가변커패시터를구현할수 있다.
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