파형 생성 회로
    31.
    发明公开
    파형 생성 회로 失效
    波形发生电路

    公开(公告)号:KR1020100068746A

    公开(公告)日:2010-06-24

    申请号:KR1020080127206

    申请日:2008-12-15

    CPC classification number: H03K4/502 H03K5/1252

    Abstract: PURPOSE: A wave generating circuit is provided to reduce manufacturing costs by reducing the size of product and the complexity of a circuit which has saw tooth waves with various slopes. CONSTITUTION: A power generator(301) generates an input voltage in order to vary the slope of a saw tooth wave according to a voltage. A controller(302) controls a power generator. A source, a gate, and a drain of a first transistor(M6) are connected to a constant voltage, the gate of a second transistor(M5), and a constant current. The source and the drain of the second transistor are connected to the constant voltage and the source of the third transistor(M4), respectively. The source and the gate of the third transistor are connected to the drain of the second transistor and the power generator, respectively. The source and the gate of a fourth transistor(M3) are connected to the source of the third transistor and the gate of a fifth transistor(M2), respectively. The source and the gate of the fifth transistor are connected to the source of the third transistor and the gate of the fourth transistor, respectively. The drain and the gate of the sixth transistor(M1) are connected to the drain of the fifth transistor and a clock generator, respectively.

    Abstract translation: 目的:提供一种波形发生电路,通过减小产品尺寸和锯齿锯齿形各种斜坡的电路的复杂性来降低制造成本。 构成:发电机(301)产生输入电压,以便根据电压改变锯齿波的斜率。 控制器(302)控制发电机。 第一晶体管(M6)的源极,栅极和漏极连接到恒定电压,第二晶体管(M5)的栅极和恒定电流。 第二晶体管的源极和漏极分别连接到恒定电压和第三晶体管(M4)的源极。 第三晶体管的源极和栅极分别连接到第二晶体管和发电机的漏极。 第四晶体管(M3)的源极和栅极分别连接到第三晶体管的源极和第五晶体管(M2)的栅极。 第五晶体管的源极和栅极分别连接到第三晶体管的源极和第四晶体管的栅极。 第六晶体管(M1)的漏极和栅极分别连接到第五晶体管的漏极和时钟发生器。

    영상 추적 칩의 영상 감지 방법
    32.
    发明公开
    영상 추적 칩의 영상 감지 방법 失效
    图像跟踪芯片的图像感测方法

    公开(公告)号:KR1020100056634A

    公开(公告)日:2010-05-28

    申请号:KR1020080115524

    申请日:2008-11-20

    CPC classification number: H04N7/18 H03M1/12 H04N5/235 H04N7/014

    Abstract: PURPOSE: An image sensing method of an image tracking chip is provided to contain an image tracking solution inside a chip by drastically reducing an image frame memory size through a sub-sampling and a timing sharing method. CONSTITUTION: Image data converted into a digital signal is inputted(S110). After luminance data is 1/2 sampled among the inputted video data, the sampled luminance data is stored(S120). A color sense among the inputted video data is outputted. While color sense data is outputted, the stored luminance data and presently inputted luminance data are compared(S130). A motion vector is outputted by calculating movement of an object(S140).

    Abstract translation: 目的:提供一种图像跟踪芯片的图像感测方法,通过采用子采样和定时共享方法大大降低图像帧存储器大小,从而在芯片内部包含图像跟踪解决方案。 构成:转换为数字信号的图像数据被输入(S110)。 在输入的视频数据中对亮度数据进行1/2采样之后,存储采样的亮度数据(S120)。 输出输入的视频数据之间的色感。 当输出色觉数据时,比较存储的亮度数据和当前输入的亮度数据(S130)。 通过计算物体的移动来输出运动矢量(S140)。

    픽셀 블록화 방법 및 이를 이용한 버퍼링 장치 및 그 방법
    33.
    发明公开
    픽셀 블록화 방법 및 이를 이용한 버퍼링 장치 및 그 방법 失效
    用于制造像素块的方法及其使用装置和缓冲方法

    公开(公告)号:KR1020080058135A

    公开(公告)日:2008-06-25

    申请号:KR1020070047275

    申请日:2007-05-15

    CPC classification number: G06T1/20 G06T15/405 G06T2200/04 G06T2207/10028

    Abstract: A method for creating a pixel block and a buffering apparatus and method using the same are provided to create data blocks by unit to create block information, and determine whether to transmit pixel data using the created block information, thereby reducing the amount of data transmission and performing buffering without unnecessary operation. A method for creating a pixel block comprises the following steps of: storing the number of pixels included into a block and the shape information of the block(701); creating pixel blocks based on the reference information(702); generating block information about the block and transmitting the generated block information to a z-buffering apparatus(703); checking whether the z-buffering apparatus requests the transmission stoppage of pixel depth values(704); transmitting the pixel depth values of the block in order if the transmission stoppage of the pixel depth values is not requested(705); and closing the pixel block generation if there is a residual block(706); and selecting a next block if there is the residual block(707).

    Abstract translation: 提供了一种用于创建像素块的方法和使用其的缓冲装置和方法,以便单元创建数据块以创建块信息,并且使用所创建的块信息来确定是否发送像素数据,从而减少数据传输量,并且 执行缓冲而不需要不必要的操作。 一种用于创建像素块的方法包括以下步骤:存储包括在块中的像素数和块的形状信息(701); 基于所述参考信息创建像素块(702); 产生关于块的块信息并将生成的块信息发送到z缓冲装置(703); 检查z缓冲装置是否请求像素深度值的传输停止(704); 如果不请求像素深度值的传输停止,按顺序传输块的像素深度值(705); 以及如果存在残余块,则关闭所述像素块生成(706); 以及如果存在剩余块,则选择下一个块(707)。

    주파수 혼합기
    34.
    发明授权
    주파수 혼합기 失效
    混频器

    公开(公告)号:KR101279986B1

    公开(公告)日:2013-07-05

    申请号:KR1020090127219

    申请日:2009-12-18

    Abstract: 본 발명에 따른 주파수 혼합기는, 알에프 신호를 입력받고, 상기 알에프 신호의 전압에 대응하는 전류를 출력하는 트랜스컨덕턴스단, 상기 알에프 신호를 중간 주파수 신호로 변조하기 위하여 상기 트랜스컨덕턴스단으로부터 출력된 상기 전류를 국부 발진 신호에 응답하여 스위칭하는 스위칭단, 상기 스위칭단과 전원 단자 사이에 연결된 부하단, 상기 스위칭단과 상기 전원 단자 사이에 연결되고, 상기 알에프 신호를 입력받아 상기 트랜스컨덕턴스단과 상보적으로 활성화됨으로써 블리딩 전류원을 발생하고, 상기 블리딩 전류원에 발생하는 잡음 제거를 위한 하나의 공진 인덕터를 갖는 커런트 블리딩단, 및 상기 트랜스컨덕턴스단과 접지 사이에 연결되고, 상기 트랜스컨덕턴스단에 안정적인 전류 흐름을 위한 적어도 하나의 전류원을 갖는 바이어스단을 포함한다. 본 발명의 주파수 혼합기는, 트랜스컨덕턴스단과 인버터 구조의 커런트 블리딩단을 구비함으로써, 변환 이득 및 주파수 대역을 증가시킨다. 또한, 본 발명의 주파수 혼합기는 하나의 공진 인덕터로 구현된 커런트 블리딩단을 구비함으로써 잡음 특성을 향상시키면서도 점유 면적을 최소화시키고, 스위칭 바이어스를 통하여 잡음을 제거할 수 있다.
    주파수 혼합기, 변환 이득, 커런트 블리딩, 공진 인덕터, 스위칭 바이어스

    Abstract translation: 混频器在根据本发明,接收RF信号,其输出的电流对应于RF信号,其中,从所述跨导级的RF信号的电流输出来调制中频信号的电压跨导级 连接在切换单元和电源端子之间的切换单元,连接在切换单元和电源单元之间的切换单元,切换单元接收RF信号并且与跨导单元互补地激活, 产生的电流源,并且被连接在电流释放阶段之间,并且所说跨导级和地具有用于发生的释放电流源中的噪声减少,至少一个电流源为电流到跨导级的稳定流量的单个谐振电感 < 它包括舞台。 本发明的混频器包括逆变器结构的跨导级和电流泄放级,由此增加转换增益和频带。 此外,本发明的混频器具有由单个谐振电感器实现的电流放电阶段,从而使占用面积最小化,同时改善噪声特性,并通过开关偏置消除噪声。

    3단계 코어스 튜닝 기법이 적용된 광대역 능동 인덕터를 사용하는 디지털 제어 발진 방법 및 장치
    35.
    发明公开
    3단계 코어스 튜닝 기법이 적용된 광대역 능동 인덕터를 사용하는 디지털 제어 발진 방법 및 장치 无效
    使用宽带激活电感器进行数字控制振荡的方法和装置,具有3级脉冲调谐

    公开(公告)号:KR1020120023997A

    公开(公告)日:2012-03-14

    申请号:KR1020100086499

    申请日:2010-09-03

    Abstract: PURPOSE: A method and an apparatus for digital-controlled oscillation using wide band active inductors with a 3-step coarse tuning manner are provided to have wide band tuning domain using a 3-step coarse tuning manner. CONSTITUTION: A digital-controlled oscillator core(310) comprises a cap bank, an active inductor, a manual inductor, and a negative GM circuit. A coarse tuning digital controller(320) controls 3-step coarse tuning operation of a digital-controlled oscillator(300). The DCO_OUT and the DCO_OUTB outputted in the digital-controlled oscillator core are dispensed through a 4(or 8)-divider(340). The outputted SDM_CLK is inputted to a sigma-DELTA modulator(330).

    Abstract translation: 目的:提供一种使用三段式粗调方式的宽带有源电感器进行数字振荡的方法和装置,以使用3步粗调方式进行宽带调谐。 构成:数字控制振荡器芯(310)包括盖组,有源电感,手动电感和负GM电路。 粗调数字控制器(320)控制数字控制振荡器(300)的三步粗调操作。 在数字控制的振荡器核心中输出的DCO_OUT和DCO_OUTB通过4(或8)分频器(340)分配。 输出的SDM_CLK被输入到Σ-DELTA调制器(330)。

    스위칭 커패시터
    36.
    发明公开
    스위칭 커패시터 无效
    开关电容器

    公开(公告)号:KR1020110085702A

    公开(公告)日:2011-07-27

    申请号:KR1020100005620

    申请日:2010-01-21

    CPC classification number: H03B5/1265 H03B5/1206 H03B5/1228

    Abstract: PURPOSE: A switching capacitor is provided to use the difference between an inversion mode capacitor and an accumulation mode capacitor, thereby increasing resolution without additional costs. CONSTITUTION: An inverter(INV) receives and inverts a bit control signal. A first transistor(P1) comprises a drain, a source, and a body connected to a common node and a gate which receives output of an inverter. A second transistor(P2) includes a drain, a source, and a body which receive the control signal and a gate connected to the common node. The first and second transistors differently operate. The first and second transistors connect a drain, a source, and a body to efficiently adjust a capacitor value in a high frequency domain.

    Abstract translation: 目的:提供开关电容器以使用反相模式电容器和累积模式电容器之间的差异,从而增加分辨率而不需要额外的成本。 构成:逆变器(INV)接收和反转位控制信号。 第一晶体管(P1)包括连接到公共节点的漏极,源极和接收反相器的输出的栅极。 第二晶体管(P2)包括接收控制信号的漏极,源极和主体以及连接到公共节点的栅极。 第一和第二晶体管的操作方式不同。 第一和第二晶体管连接漏极,源极和主体以有效地调节高频域中的电容器值。

    전하 펌프
    37.
    发明公开
    전하 펌프 无效
    电荷泵

    公开(公告)号:KR1020110015937A

    公开(公告)日:2011-02-17

    申请号:KR1020090073394

    申请日:2009-08-10

    Abstract: PURPOSE: A charge pump is provided to adjust a voltage in various voltage rates regardless of the limitation related to the capacitance of capacitors and the number of capacitors. CONSTITUTION: A first switch is turned on or turned off according to a first charging voltage. A second switch is turned on or turned off according to a second charging voltage applied to a gate. A first routing switch provides the output voltage routing of the sum of the first charging voltage and a voltage charged in a second capacitor in case the first switch is turned off. A second routing switch provides the output voltage routing of the sum of the first charging voltage and a voltage charged in a first capacitor in case of the second switch is turned off. A first level shifter(230) and a second level shifter(235) correct voltage loss of the first routing switch and the second routing switch.

    Abstract translation: 目的:提供电荷泵来调节各种电压速率的电压,而不管与电容器的电容和电容器数量有关的限制。 构成:第一个开关根据第一个充电电压开启或关闭。 根据施加到门的第二充电电压,第二开关导通或关断。 在第一开关断开的情况下,第一路由开关提供第一充电电压和充电在第二电容器中的电压之和的输出电压路由。 在第二开关断开的情况下,第二路由选择开关提供第一充电电压和第一电容器充电的电压之和的输出电压路由。 第一电平移位器(230)和第二电平移位器(235)校正第一路由交换机和第二路由交换机的电压损耗。

    능동 인덕터
    38.
    发明公开
    능동 인덕터 失效
    主动电感器

    公开(公告)号:KR1020100099873A

    公开(公告)日:2010-09-15

    申请号:KR1020090018429

    申请日:2009-03-04

    CPC classification number: H03H11/48 H01L27/02 H01L27/04 H03B5/08

    Abstract: PURPOSE: An active inductor is provided to vary the Q-factor, inductance, magnetic-resonance frequency of inputted impedance by maintaining the total consumption amount of a current while voltages in both ends of a varactor are varied. CONSTITUTION: Current source(I1) is connected between a VDD and a V2 node. The current source is composed of a p-metal oxide semiconductor field effect transistor(MOSFET). The amount of a current is controlled by a voltage applied to the gate of the p-MOSFET. A first n-MOSFET(M1) includes a drain connected with the V2 node, a source connected with a ground, and a gate connected with a V1 node. A second n-MOSFET(M2) includes a drain connected with the VDD, a source connected with the V1 node, and a gate connected with one end of a first resistance(R1). The first resistance is connected between the V2 node and the second n-MOSFET. A second resistance(R2) is connected between the V1 node and the ground. A varactor(Cvar1) is connected between the V2 node and the ground.

    Abstract translation: 目的:提供有源电感器,通过在变容二极管两端的电压变化的同时保持电流的总消耗量来改变输入阻抗的Q因子,电感,磁共振频率。 构成:电流源(I1)连接在VDD和V2节点之间。 电流源由p金属氧化物半导体场效应晶体管(MOSFET)组成。 电流的量由施加到p-MOSFET的栅极的电压控制。 第一n-MOSFET(M1)包括与V2节点连接的漏极,与地连接的源极和与V1节点连接的栅极。 第二n-MOSFET(M2)包括与VDD连接的漏极,与V1节点连接的源极和与第一电阻(R1)的一端连接的栅极。 第一个电阻连接在V2节点和第二个n-MOSFET之间。 第二个电阻(R2)连接在V1节点和地之间。 变容二极管(Cvar1)连接在V2节点和地之间。

    배터리 충전기
    39.
    发明授权
    배터리 충전기 失效
    充电器

    公开(公告)号:KR100974313B1

    公开(公告)日:2010-08-10

    申请号:KR1020080028073

    申请日:2008-03-26

    Abstract: 본 발명의 배터리 충전기는 제 1 충전 모드 구간 동안 스위칭 충전기로서 동작하는 제 1 충전기, 그리고 제 2 충전 모드 구간 동안 리니어 충전기로서 동작하는 제 2 충전기를 포함하며, 상기 제 1 충전기와 상기 제 2 충전기는 피드백 루프의 적어도 일부를 공유한다.
    배터리 충전기, 스위칭 충전기, 리니어 충전기

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