公开(公告)号：EP2368262B1

公开(公告)日：2017-03-08

申请号：EP09797035.4

申请日：2009-12-18

Applicant: 3D Plus

Inventor： VAL, Christian ,  COUDERC, Pascal ,  VAL, Alexandre

IPC: H01L21/60 ,  H01L21/683 ,  H05K3/32 ,  H01L21/56 ,  H05K1/14 ,  H05K1/18

CPC classification number: H01L21/6835 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/96 ,  H01L2221/68377 ,  H01L2224/04105 ,  H01L2224/13139 ,  H01L2224/16 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/81201 ,  H01L2224/81801 ,  H01L2224/838 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K1/141 ,  H05K1/185 ,  H05K3/321 ,  H05K2203/1469 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2224/0401

公开(公告)号：EP1864326B1

公开(公告)日：2012-11-14

申请号：EP06725523.2

申请日：2006-04-03

Applicant: 3D Plus

Inventor： VAL, Christian

IPC: H01L23/498 ,  H05K3/34 ,  H01L25/16

CPC classification number: H01L23/4985 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/5387 ,  H01L25/105 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/19041 ,  H05K1/116 ,  H05K1/189 ,  H05K3/3436 ,  H05K2201/09572 ,  H05K2201/09663 ,  H05K2203/041 ,  H05K2203/0455 ,  Y02P70/613 ,  H01L2924/00

公开(公告)号：EP2126969A1

公开(公告)日：2009-12-02

申请号：EP08708288.9

申请日：2008-01-28

Applicant: 3D Plus

Inventor： VAL, Christian

IPC: H01L21/60 ,  H01L23/48 ,  H01L25/065 ,  H01L21/98

CPC classification number: H01L24/81 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16146 ,  H01L2224/81224 ,  H01L2224/8184 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  Y10T29/49126 ,  Y10T29/49165 ,  Y10T29/49167 ,  H01L2924/00 ,  H01L2924/00014

Abstract: The invention relates to a method of interconnecting electronic components of a first wafer (T1) with electronic components of a second wafer (T2), each wafer comprising metallized vias (1) which pass through the thickness of the wafer. The method comprises the following steps of: Depositing a drop (3) of conducting ink containing solvents and nanoparticles of metal onto each via (1) of the first wafer (T1), stacking the second wafer (T2) on the first in such a way that the vias (1) of the second wafer (T2) are substantially overlaid on the vias (1) of the first wafer (T1). Eliminating 50 to 90% of the solvents contained in the drops (3) by heating or vacuum treatment so as to obtain a pasty ink, sintering the drops (3) of pasty ink by laser so as to produce electrical connections (31) between the overlaid metallized vias (1).

公开(公告)号：EP3905325A1

公开(公告)日：2021-11-03

申请号：EP21170597.5

申请日：2021-04-27

Applicant: 3D Plus

Inventor： VAL, Christian

IPC: H01L23/498

Abstract: L'invention se situe dans le domaine de la fabrication de modules électroniques 3D, compatible des composants fonctionnant au-delà de 1 GHz. L'invention concerne un module électronique 3D présentant une interconnexion entre un conducteur horizontal (31, 32 ; 33, 34) et un conducteur vertical (30) auquel il est relié présente dans un plan vertical une courbure non nulle. Elle concerne aussi le procédé de fabrication associé.

公开(公告)号：EP3417481B1

公开(公告)日：2020-03-25

申请号：EP17704275.1

申请日：2017-02-14

Applicant: 3D Plus

Inventor： VAL, Christian

IPC: H01L25/065 ,  H01L21/98 ,  H01L23/49 ,  H01L21/60 ,  H01L23/66

公开(公告)号：EP3417481A1

公开(公告)日：2018-12-26

申请号：EP17704275.1

申请日：2017-02-14

Applicant: 3D Plus

Inventor： VAL, Christian

IPC: H01L25/065 ,  H01L23/49 ,  H01L21/60

Abstract: The invention relates to a 3D electronic module comprising, along a so-called vertical direction, a stack (4) of electronic slices (16), each slice comprising at least one chip (1) furnished with interconnection pads (10), this stack being assembled to an interconnection circuit (2) of the module furnished with connection balls, the pads (10) of each chip being connected by electrical wiring leads (15) to vertical buses (41) that are in turn electrically linked to the module interconnection circuit (2), a wiring lead and the vertical bus to which it is linked forming an electrical conductor between a pad of a chip and the interconnection circuit, characterized in that each electrical wiring lead (15) is linked to its vertical bus (41) while forming an oblique angle (α2) in a vertical plane and in that the length of the wiring lead between a pad of a chip of one slice and the corresponding vertical bus is different from the length of the wiring lead between the same pad of a chip of another slice and the corresponding vertical bus, obtained by a non-rectilinear wiring of the wiring lead so as to compensate for the difference in vertical length of the vertical bus from slice to slice, in such a way that the electrical conductor between the pad of a chip of a slice and the interconnection circuit, and the electrical conductor between the same pad of a chip of the other slice and the interconnection circuit, have the same length.

公开(公告)号：EP3261116A1

公开(公告)日：2017-12-27

申请号：EP17175943.4

申请日：2017-06-14

Applicant: 3D Plus

Inventor： VAL, Christian

IPC: H01L21/56 ,  H01L23/31 ,  H01L25/03 ,  H01L25/10

CPC classification number: H01L21/6835 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3135 ,  H01L24/06 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2225/1035 ,  H01L2924/142 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/18165 ,  H01L2924/3511 ,  H05K3/321 ,  H01L2924/00014 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/00

Abstract: L'invention a pour objet un procédé de fabrication collective de modules électroniques 3D, chaque module électronique 3D comprenant un empilement d'au moins deux boîtiers électroniques à billes, reportables en surface, testés à leur température et fréquence de fonctionnement. Il comprend :
- une étape de fabrication de plaques reconstituées, chaque plaque reconstituée étant fabriquée selon les sous-étapes suivantes dans l'ordre suivant :
∘ A1) les boîtiers électroniques sont posés sur une première peau collante côté billes,
∘ B1) moulage des boîtiers électroniques dans la résine et polymérisation de la résine, pour obtenir la plaque intermédiaire,
o C1) amincissement de la plaque intermédiaire sur la face de la plaque intermédiaire opposée aux billes,
∘ D1) retrait de la première peau collante et pose de la plaque intermédiaire sur une deuxième peau collante, côté opposé aux billes,
∘ E1) amincissement de la plaque intermédiaire sur la face côté billes,
∘ F1) formation d'une couche de redistribution côté billes,
∘ G1) retrait de la deuxième peau collante pour obtenir une plaque reconstituée d'épaisseur inférieure à l'épaisseur d'origine des boîtiers électroniques,

- plusieurs plaques reconstituées ayant été obtenues à l'issue des sous-étapes précédentes, empilement des plaques reconstituées,
- découpe des plaques reconstituées empilées pour obtenir des modules 3D.

Abstract translation: 本发明涉及的三维电子模块的大容量的制造方法，每个3D电子模块，其包括至少两个控制单元轴承的堆叠，结转表面，在该温度和工作频率进行测试。 它包括： - 使重组板的步骤中，每个板被按照以下顺序的下列子步骤重建制造：∘A1）的电子单元被放置在第一侧上的皮肤粘性珠，∘B1）成型 控制单元在所述树脂和在面板相对的中间的到珠子上，∘D1）去除所述第一粘合剂的皮肤和安装板固化该树脂，以获得中间板，邻C1）变薄中间板的 中间上的相反侧的第二粘皮到珠子上，∘E1）上的前侧轴承，∘F1）形成再分布层侧珠，∘G1）中间板变薄去除第二粘性皮肤以获得 厚度小于电子盒原始厚度的重组板， - 几个重构板，具有 TY在之前的子步骤的结束时获得，堆叠板重构， - 堆叠以获得重建的3D模块板的切削加工。

公开(公告)号：EP2705531A2

公开(公告)日：2014-03-12

申请号：EP12718241.8

申请日：2012-05-04

Applicant: 3D Plus

Inventor： VAL, Christian

IPC: H01L23/538 ,  H01L21/60 ,  H01L23/48 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01G4/224 ,  B05D1/02 ,  B05D5/10 ,  C23C14/08 ,  C23C16/01 ,  C23C16/402 ,  H01L21/568 ,  H01L23/3121 ,  H01L24/18 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68368 ,  H01L2224/24227 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01079 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/181 ,  H05K1/115 ,  H05K1/181 ,  H05K3/284 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/82

Abstract: The invention relates to a method for the collective production of a reconstituted wafer that comprises chips with connection pads on a so-called front side of the chip, said method comprising a step of: A) placing the chips on an initial adhesive carrier, front side on the carrier, characterized in that it comprises the following steps: B) depositing, in the gaseous phase at atmospheric pressure and at room temperature, an electrically insulating layer on the initial carrier and the chips, this layer having a mechanical role in supporting the chips; C) transferring the chips covered with the mineral layer to a temporary adhesive carrier, the rear side of the chips facing the temporary adhesive carrier; D) removing the initial adhesive carrier; E) placing the chips on a chuck, the front sides of the chips facing the chuck; F) removing the temporary adhesive carrier; G) depositing a resin over the chuck so as to encapsulate the chips, then curing the resin; H) removing the chuck; and I) producing an RDL on the active side.

公开(公告)号：EP2441088A1

公开(公告)日：2012-04-18

申请号：EP10725161.3

申请日：2010-06-14

Applicant: 3D Plus

Inventor： VAL, Christian

IPC: H01L23/31 ,  H01L23/538 ,  H01L21/56

CPC classification number: H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00

Abstract: The invention relates to a method for manufacturing a reconstituted wafer (100) which comprises chips (1) with bonding pads (10), said method including the following steps of manufacturing a first chip wafer (1). The method also includes the following steps: producing on said wafer a stack of at least one layer for redistributing the pads (10) of the chips on conductive tracks (12) intended for interconnecting chips, said stack being referred to as the main RDL layer (14); cutting said wafer in order to obtain individual chips (1) each with its own RDL layer (14); adding individual chips with RDL layers (14) to a substrate (20) that is rigid enough to remain flat during subsequent steps, and provided with a layer of adhesive (21), with the RDL layer (14) on the layer of adhesive (21); depositing a resin (30) in order to encapsulate the chips (1); polymerising the resin; removing the rigid substrate (20); depositing a single redistribution layer referred to as mini RDL (24) to connect the conductive tracks of the main RDL layer (14) with interconnecting contacts, via openings (22) made in the layer of adhesive (21), the wafer comprising the polymerised resin, the chips with the RDL layer thereof and the mini RDL forming the reconstituted wafer (100).

公开(公告)号：EP2406815A1

公开(公告)日：2012-01-18

申请号：EP10708971.6

申请日：2010-03-09

Applicant: 3D Plus

Inventor： VAL, Christian

IPC: H01L21/56 ,  B81C1/00

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/4334 ,  H01L24/24 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/24137 ,  H01L2224/24998 ,  H01L2224/32245 ,  H01L2224/73217 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2225/1094 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: The invention relates to a method for producing a reconstituted board (1) that comprises chips (10) having connection pads (11) on a surface of said chip, referred to as a front surface (12), wherein the method includes the following steps: positioning the chips (10) on an adhesive substrate (20) with the front surface on the substrate, depositing a resin (50) onto the substrate (20) for encapsulating the chips, and polymerising the resin (50). Before the resin deposition step, the method includes a step of gluing a supporting plate (40) onto the chips for positioning the chips, said supporting plate (40) including portions provided on a surface (12, 13) of the chips.