公开(公告)号：FR2857157B1

公开(公告)日：2005-09-23

申请号：FR0307977

申请日：2003-07-01

Applicant: 3D PLUS SA

Inventor： VAL CHRISTIAN ,  LIGNIER OLIVIER

IPC: H01L21/60 ,  H01L21/68 ,  H01L21/98 ,  H01L23/538 ,  H01L25/16 ,  H01L21/58 ,  H01L23/52

Abstract: A method for interconnecting active and passive components in two or three dimensions, and the resulting thin heterogeneous components. The method comprises: positioning and fixing (11) at least one active component and one passive component on a flat support (23), the terminals being in contact with the support, depositing (12) a polymer layer (24) on all of the support and the components, removing the support (14), redistributing the terminals (15) between the components and/or toward the periphery by metal conductors (26) arranged in a predetermined layout, making it possible to obtain a heterogeneous reconstituted structure, heterogeneously thinning (16) the structure by nonselective surface treatment of the polymer layer and at least one passive component (22).

公开(公告)号：FR2832136B1

公开(公告)日：2005-02-18

申请号：FR0114543

申请日：2001-11-09

Applicant: 3D PLUS SA

Inventor： VAL CHRISTIAN

IPC: G02B6/42 ,  B81B7/00 ,  B81B7/02 ,  H01L23/10 ,  H01L23/31 ,  H01L23/34 ,  H01L31/0203 ,  H01L31/024 ,  B65D85/00 ,  B65B31/00

Abstract: The invention relates to a device for the hermetic encapsulation of a component that has to be protected from any stress. The component (5) is fastened to a substrate (15) that carries, on its other face, a temperature-regulating element (17) fastened by adhesive bonding (16). This assembly is placed in a package comprising two portions (11, 12) joined together by adhesive bonding (13) with a passage for optical links (6) and for electrical connections (18, 142). It is supported by protuberances (19) of one portion (11) of the package. Bonded to the other portion (12) is a three-dimensional interconnection block (14) forming the temperature-regulating electronics. The block, the package (11, 12) and a minimum length (L) of the links and connections are encapsulated in a mineral protective layer (4'). The invention applies especially to optoelectronic components and to MEMS components.

公开(公告)号：FR2812453B1

公开(公告)日：2004-08-20

申请号：FR0009731

申请日：2000-07-25

Applicant: 3D PLUS SA

Inventor： VAL CHRISTIAN

IPC: H01G4/33 ,  H01G4/40 ,  H01L23/522 ,  H01L23/552 ,  H01L23/58 ,  H01L23/64 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L21/762

Abstract: The invention relates to a process for the distributed shielding and decoupling of an electronic device having integrated components with three-dimensional interconnection, to such a device and to a production process. The device comprises, associated with each active component (2), at least one capacitor plane formed from a thin sheet (10) of a dielectric, said sheet being metallized (10, 11, 12) on its two plane faces. The components and the capacitor planes are stacked in alternation and joined together to form a block (1'), the lateral faces (21 to 24) of which carry conductors (13, 14) ensuring 3D interconnection. The metallizations (11, 12) are delimited in order to be flush with the edges of the block only via tabs (110, 120). One of the metallizations (11) connected to ground serves as shielding. The invention applies especially to the production of very compact memory blocks.

公开(公告)号：FR2812453A1

公开(公告)日：2002-02-01

申请号：FR0009731

申请日：2000-07-25

Applicant: 3D PLUS SA

Inventor： VAL CHRISTIAN

IPC: H01G4/33 ,  H01G4/40 ,  H01L23/522 ,  H01L23/552 ,  H01L23/58 ,  H01L23/64 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L21/762

Abstract: The invention concerns a method for distributed shielding and bypass for an electronic device with integrated components having three-dimensional interconnection, the inventive device and a method for making same. The device comprises, associated with each active component (2), at least a capacitor plane consisting of a thin foil (10) made of metal-coated dielectric material (11, 12) on its two planar surfaces. The components and capacitor planes are stacked and alternately assembled to form a block (1') whereof the side surfaces (21 to 24) bear conductors (13, 14) providing the three-dimensional interconnection. The metal coatings (11, 12) are delimited to be flush with the edges of the block only through tabs (110, 120). One of the metal coatings (11) connected to the ground acts as shield. The invention is particularly useful for producing very compact storage blocks.

公开(公告)号：FR3077825A1

公开(公告)日：2019-08-16

申请号：FR1851215

申请日：2018-02-14

Applicant: 3D PLUS

Inventor： VAL CHRISTIAN

IPC: C23C18/52 ,  C23C18/34 ,  C23C18/40 ,  H01L21/30

Abstract: L'invention concerne un procédé de dépôt en phase liquide de couches métalliques dans des trous (11) d'un module électronique (10) disposé dans une enceinte hermétique (1), à partir d'un liquide (4) chimique à composés métalliques destinés à former une couche métallique. Les trous ont une profondeur P et un diamètre D tels que D>80 µm et P/D > 10, et le procédé comporte au moins un cycle (Cyc) comportant les sous-étapes suivantes : - M1) Mise sous une pression prédéterminée PO de l'enceinte et remplissage de l'enceinte par le liquide, - M2) Dégazage des trous par mise sous une pression réduite P1 de l'enceinte, avec P1

公开(公告)号：FR3053158B1

公开(公告)日：2018-11-16

申请号：FR1655798

申请日：2016-06-22

Applicant: 3D PLUS

Inventor： VAL CHRISTIAN

IPC: H01L21/70 ,  H01L21/66 ,  H01L25/065

公开(公告)号：FR3038130B1

公开(公告)日：2017-08-11

申请号：FR1555857

申请日：2015-06-25

Applicant: 3D PLUS

Inventor： VAL CHRISTIAN

IPC: H01L21/98 ,  H01L23/48 ,  H05K1/18

公开(公告)号：FR3034253A1

公开(公告)日：2016-09-30

申请号：FR1552457

申请日：2015-03-24

Applicant: 3D PLUS

Inventor： VAL CHRISTIAN

IPC: H01L21/02

Abstract: Dispositif (30, 50) de puce électronique (31, 51, 72) à résistance thermique améliorée, comprenant au moins un plot de connexion électrique (32, 54, 73) avec liaison d'interconnexion électrique (33, 55, 74), au moins un plot thermique (34, 61, 76) disposé sur une face de la puce, au moins un élément d'échange thermique (36, 59, 70), et au moins une liaison thermique (35, 57, 75) entre un plot thermique (34, 61, 76) et un élément d'échange thermique (36, 59, 70).

公开(公告)号：FR2974942B1

公开(公告)日：2016-07-29

申请号：FR1153902

申请日：2011-05-06

Applicant: 3D PLUS

Inventor： VAL CHRISTIAN

IPC: H01L21/56

公开(公告)号：SG176784A1

公开(公告)日：2012-01-30

申请号：SG2011091485

申请日：2010-06-14

Applicant: 3D PLUS

Inventor： VAL CHRISTIAN

Abstract: METHOD FOR POSITIONING CHIPS DURING THE PRODUCTION OF A RECONSTITUTED WAFERThe invention relates to a method for fabricating a re-built wafer (100) which comprises chips (1) having connection pads (10), this method comprising the following steps of:fabricating a first wafer of chips (1).It also comprises the following steps:production on this wafer of a stack of at least one layer of redistribution of the pads (10) of the chips on conductive tracks (12) designed for the interconnection of the chips, this stack being designated the main RDL layer (14),cutting this wafer in order to obtain individual chips (1) eachfurnished with their RDL layer (14),transferring the individual chips with their RDL layer (14) to a sufficiently rigid support (20) to remain flat during the following steps, which support is furnished with an adhesive layer (21), with the RDL layer (14) on the adhesive layer (21),depositing a resin (30) in order to encapsulate the chips (1), polymerizing the resin,removing the rigid support (20),depositing a single redistribution layer called a mini RDL (24) in order to connect the conductive tracks of the main RDL layer (14) up to interconnection contacts, through apertures (22) made in the adhesive layer (21), the wafer comprising the polymerized resin, the chips with their RDL layer and the mini RDL being the re-built wafer (100).No FIGURE