公开(公告)号：EP1019914B1

公开(公告)日：2002-03-06

申请号：EP98919745.4

申请日：1998-04-10

Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED

Inventor： CHEN, Pau-Ling ,  VAN BUSKIRK, Michael ,  HOLLMER, Shane, Charles ,  LE, Bing, Quang ,  KAWAMURA, Shoichi/ c/o Fujitsu Limited ,  HU, Chung-You ,  SUN, Yu ,  HADDAD, Sameer ,  CHANG, Chi

IPC: G11C16/04

CPC classification number: G11C16/0483

Abstract: A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.

公开(公告)号：EP0835509B1

公开(公告)日：1999-08-11

申请号：EP96922505.1

申请日：1996-06-18

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HADDAD, Sameer ,  CHANG, Chi ,  LIU, David, K., Y.

IPC: G11C16/06

CPC classification number: G11C16/10

Abstract: Disclosed herein is a channel hot-carrier page write method including an array of stacked gate flash EEPROM memory cells operating in a very low energy programming mode permitting page writing of 1024 bits within a 20-100 mu S programming interval. Internal programming voltage levels are derived from on-chip circuits, such as charge pumps (272), operated from a single +Vcc source. In a preferred embodiment, a cache memory (262) buffers data transfers between a computer bus (264) and the page oriented storage array (252). In another embodiment, core doping is increased in the channel and drain regions to enhance hot carrier injection and to lower the programming drain voltage. The stacked floating gate structure is shown to exhibit a high programming efficiency in a range from 10 to 10 at drain voltages below 5.2VDC. In another embodiment AC components of the programming current are minimized by precharging a common source line at the start of a programming cycle.

公开(公告)号：EP0907956A1

公开(公告)日：1999-04-14

申请号：EP97917123.0

申请日：1997-03-28

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HU, Chung-You ,  SUN, Yu ,  HADDAD, Sameer ,  CHANG, Chi

IPC: G11C16

CPC classification number: G11C16/0483

Abstract: The present invention facilitates programming of selected floating gate devices while successfully inhibiting the programming of unselected devices, without the need for growing multiple thicknesses of oxides. The preferred embodiment of the present invention utilizes a multiple select gate device. In particular, the select gate device is preferably a dual floating gate device rather than the conventional transistor (or device functioning as a conventional transistor) used in the current Flash memory systems as a select gate device.

公开(公告)号：EP0819308A1

公开(公告)日：1998-01-21

申请号：EP95943963.0

申请日：1995-12-22

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HADDAD, Sameer ,  FANG, Hao

IPC: G11C16

CPC classification number: G11C16/3477 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3427 ,  G11C16/3486 ,  G11C2216/16 ,  G11C2216/18

Abstract: There is provided an improved method for bulk (or byte) programming an array of flash EEPROM memory cells. A negative voltage is applied to the substrate of the array. A reference voltage of zero volts is applied simultaneously to the drain regions of selected memory cells that are to be programmed. There is also applied simultaneously the same reference voltage of zero volts to the control gates of the selected memory cells. The present invention provides for low current consumption and fast programming of the memory cell, which require only a single, low voltage power supply. The endurance reliability is greater than 100,000 cycles.