公开(公告)号：WO1997016852A1

公开(公告)日：1997-05-09

申请号：PCT/US1996014316

申请日：1996-09-06

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LIU, David, K., Y. ,  KUAN, Ming, Sang ,  CHANG, Chi

IPC: H01L27/02

CPC classification number: H01L27/0266 ,  Y10S438/982

Abstract: A method for reducing encroachment of an impurity implant into a channel region in a non-ESD transistor in a semiconductor circuit, the non-ESD transistor receiving both first and second implant dopants, and the circuit including a plurality of ESD transistors includes forming the ESD transistors of the circuit at a predetermined angular offset from the non-ESD transistor, and performing the second dopant implant at a predetermined tilt implant angle, wherein the non-ESD transistor has reduced encroachment of the impurity implant. A plurality of transistors formed on a semiconductor wafer include a plurality of non-ESD transistors, the plurality of non-ESD transistors including spacer regions and impurity implant regions encroaching the spacer regions, and a plurality of ESD transistors, the plurality of ESD transistors formed at a predetermined angular offset from the non-ESD transistors. Further, the plurality of ESD transistors include the spacer regions and impurity implant regions encroaching the spacer regions further than the impurity implant regions of the non-ESD transistors.

Abstract translation: 一种用于将杂质注入减少到半导体电路中的非ESD晶体管中的沟道区域的方法，所述非ESD晶体管接收第一和第二注入掺杂剂，并且包括多个ESD晶体管的电路包括形成ESD 晶体管，其以非ESD晶体管的预定角度偏移，并以预定的倾斜注入角执行第二掺杂剂注入，其中非ESD晶体管具有减少的杂质注入侵入。 形成在半导体晶片上的多个晶体管包括多个非ESD晶体管，所述多个非ESD晶体管包括间隔区域和侵入间隔区域的杂质注入区域，以及多个ESD晶体管，所述多个ESD晶体管形成 在非ESD晶体管的预定角度偏移处。 此外，多个ESD晶体管包括比非ESD晶体管的杂质注入区域更远的间隔区域和杂质注入区域。

公开(公告)号：WO1997001172A1

公开(公告)日：1997-01-09

申请号：PCT/US1996010562

申请日：1996-06-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HADDAD, Sameer ,  CHANG, Chi ,  LIU, David, K., Y.

IPC: G11C16/06

CPC classification number: G11C16/10

Abstract: Disclosed herein is a channel hot-carrier page write method including an array of stacked gate flash EEPROM memory cells operating in a very low energy programming mode permitting page writing of 1024 bits within a 20-100 mu S programming interval. Internal programming voltage levels are derived from on-chip circuits, such as charge pumps (272), operated from a single +Vcc source. In a preferred embodiment, a cache memory (262) buffers data transfers between a computer bus (264) and the page oriented storage array (252). In another embodiment, core doping is increased in the channel and drain regions to enhance hot carrier injection and to lower the programming drain voltage. The stacked floating gate structure is shown to exhibit a high programming efficiency in a range from 10 to 10 at drain voltages below 5.2VDC. In another embodiment AC components of the programming current are minimized by precharging a common source line at the start of a programming cycle.

Abstract translation: 这里公开了一种通道热载体页写入方法，其包括以非常低能量编程模式操作的堆叠栅极快闪EEPROM存储器单元的阵列，允许在20-100μs编程间隔内进行1024位的写入。 内部编程电压电平源自片上电路，例如从单个+ Vcc源运行的电荷泵（272）。 在优选实施例中，高速缓冲存储器（262）缓冲计算机总线（264）和面向页面的存储阵列（252）之间的数据传输。 在另一个实施例中，在沟道和漏极区域中增加了芯掺杂以增强热载流子注入并降低编程漏极电压。 堆叠的浮置栅极结构在低于5.2VDC的漏极电压下显示出在10 -6至10 -4的范围内的高编程效率。 在另一个实施例中，通过在编程周期开始时对公共源极线进行预充电来最小化编程电流的AC分量。

公开(公告)号：EP0835509B1

公开(公告)日：1999-08-11

申请号：EP96922505.1

申请日：1996-06-18

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HADDAD, Sameer ,  CHANG, Chi ,  LIU, David, K., Y.

IPC: G11C16/06

CPC classification number: G11C16/10

Abstract: Disclosed herein is a channel hot-carrier page write method including an array of stacked gate flash EEPROM memory cells operating in a very low energy programming mode permitting page writing of 1024 bits within a 20-100 mu S programming interval. Internal programming voltage levels are derived from on-chip circuits, such as charge pumps (272), operated from a single +Vcc source. In a preferred embodiment, a cache memory (262) buffers data transfers between a computer bus (264) and the page oriented storage array (252). In another embodiment, core doping is increased in the channel and drain regions to enhance hot carrier injection and to lower the programming drain voltage. The stacked floating gate structure is shown to exhibit a high programming efficiency in a range from 10 to 10 at drain voltages below 5.2VDC. In another embodiment AC components of the programming current are minimized by precharging a common source line at the start of a programming cycle.

公开(公告)号：EP0835509A1

公开(公告)日：1998-04-15

申请号：EP96922505.0

申请日：1996-06-18

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HADDAD, Sameer ,  CHANG, Chi ,  LIU, David, K., Y.

IPC: G11C16

CPC classification number: G11C16/10

Abstract: Disclosed herein is a channel hot-carrier page write method including an array of stacked gate flash EEPROM memory cells operating in a very low energy programming mode permitting page writing of 1024 bits within a 20-100νS programming interval. Internal programming voltage levels are derived from on-chip circuits, such as charge pumps (272), operated from a single +Vcc source. In a preferred embodiment, a cache memory (262) buffers data transfers between a computer bus (264) and the page oriented storage array (252). In another embodiment, core doping is increased in the channel and drain regions to enhance hot carrier injection and to lower the programming drain voltage. The stacked floating gate structure is shown to exhibit a high programming efficiency in a range from 10?-6 to 10-4¿ at drain voltages below 5.2VDC. In another embodiment AC components of the programming current are minimized by precharging a common source line at the start of a programming cycle.