公开(公告)号：WO1996013057A2

公开(公告)日：1996-05-02

申请号：PCT/US1995012901

申请日：1995-09-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  FANG, Hao ,  HADDAD, Sameer ,  CHANG, Chi

IPC: H01L00/00

CPC classification number: H01L27/0251 ,  H01L27/115

Abstract: An improved non-volatile memory device (10) is provided, in which the threshold voltage variations (Vts) and transconductance degradation are significantly reduced. The NVM (10) includes protection structure (200) for limiting the process induced damage incurred during the manufacturing process. The protection structure (200) is utilized to provide reliable and stable dielectrical characteristics for the NVM device (10). The protection structure (200) is easy to implement and will not affect the conventional NVM (10) performance.

Abstract translation: 提供了一种改进的非易失性存储器件（10），其中阈值电压变化（Vts）和跨导退化明显降低。 NVM（10）包括用于限制在制造过程中产生的过程引起的损坏的保护结构（200）。 保护结构（200）用于为NVM装置（10）提供可靠和稳定的介电特性。 保护结构（200）易于实现，不会影响传统的NVM（10）性能。

公开(公告)号：WO1996026522A1

公开(公告)日：1996-08-29

申请号：PCT/US1995016805

申请日：1995-12-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HADDAD, Sameer ,  FANG, Hao

IPC: G11C16/06

CPC classification number: G11C16/3477 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3427 ,  G11C16/3486 ,  G11C2216/16 ,  G11C2216/18

Abstract: There is provided an improved method for bulk (or byte) programming an array of flash EEPROM memory cells. A negative voltage is applied to the substrate of the array. A reference voltage of zero volts is applied simultaneously to the drain regions of selected memory cells that are to be programmed. There is also applied simultaneously the same reference voltage of zero volts to the control gates of the selected memory cells. The present invention provides for low current consumption and fast programming of the memory cell, which require only a single, low voltage power supply. The endurance reliability is greater than 100,000 cycles.

Abstract translation: 提供了用于批量（或字节）编程闪存EEPROM存储器单元阵列的改进方法。 对阵列的衬底施加负电压。 将零编程的参考电压同时施加到要编程的所选存储单元的漏极区域。 同时也向所选择的存储器单元的控制栅极同时施加零伏特的相同参考电压。 本发明提供了仅需要单个低电压电源的存储单元的低电流消耗和快速编程。 耐久可靠性大于100,000次。

公开(公告)号：EP0763258B1

公开(公告)日：2000-07-12

申请号：EP95936270.8

申请日：1995-09-29

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： FANG, Hao ,  HADDAD, Sameer ,  CHANG, Chi

IPC: H01L27/02 ,  H01L27/115 ,  G11C5/00

CPC classification number: H01L27/0251 ,  H01L27/115

Abstract: An improved non-volatile memory device (10) is provided, in which the threshold voltage variations (Vts) and transconductance degradation are significantly reduced. The NVM (10) includes protection structure (200) for limiting the process induced damage incurred during the manufacturing process. The protection structure (200) is utilized to provide reliable and stable dielectrical characteristics for the NVM device (10). The protection structure (200) is easy to implement and will not affect the conventional NVM (10) performance.

公开(公告)号：EP0763258A2

公开(公告)日：1997-03-19

申请号：EP95936270.0

申请日：1995-09-29

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： FANG, Hao ,  HADDAD, Sameer ,  CHANG, Chi

IPC: H01L27

CPC classification number: H01L27/0251 ,  H01L27/115

Abstract: An improved non-volatile memory device (10) is provided, in which the threshold voltage variations (Vts) and transconductance degradation are significantly reduced. The NVM (10) includes protection structure (200) for limiting the process induced damage incurred during the manufacturing process. The protection structure (200) is utilized to provide reliable and stable dielectrical characteristics for the NVM device (10). The protection structure (200) is easy to implement and will not affect the conventional NVM (10) performance.

公开(公告)号：EP1261987A2

公开(公告)日：2002-12-04

申请号：EP01931109.1

申请日：2001-03-05

Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED

Inventor： HAN, K., Michael ,  FANG, Hao ,  HIGASHITANI, Masaaki

IPC: H01L21/28 ,  H01L21/8247 ,  H01L29/788 ,  H01L27/115

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524

Abstract: A single tunnel gate oxidation process for fabricating NAND memory strings where the gate oxide (24) of the select transistors and the floating gate memory transistors are fabricated in a single oxidation step is disclosed. The select gate transistors and the floating gate memory transistors have an oxide thickness of 85Å-105Å. For single tunnel gate approach, a careful selection of the medium doped source/drain region (62) implant conditions is necessary for proper function of the NAND memory string. In one embodiment, the medium doped source/drain region is doped with Arsenic to a concentration of 10?13-1014/cm2¿.

公开(公告)号：EP1204989A1

公开(公告)日：2002-05-15

申请号：EP00943317.8

申请日：2000-06-29

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： AU, Kenneth, Wo-Wai ,  CHANG, Kent, Kuohua ,  FANG, Hao

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11524

Abstract: In one embodiment, the present invention relates to a method of forming a NAND type flash memory device, involving the steps of growing a first oxide layer over at least a portion of a substrate, the substrate including a flash memory cell area and a select gate area; removing a portion of the first oxide layer in the flash memory cell area of the substrate; growing a second oxide layer over at least a portion of the substrate in the flash memory cell area and over at least a portion of the a first oxide layer in the select gate area; depositing a first in situ doped amorphous silicon layer over at least a portion of the second oxide layer, the first in situ doped amorphous silicon layer having a thickness from about 400 to about 1,000; depositing a dielectric layer over at least a portion of the first in situ doped amorphous silicon layer; depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer; and forming a flash memory cell in the flash memory cell area of the substrate and a select gate transistor in the select gate area substrate, the flash memory cell comprising the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer, and the select gate transistor comprising the first oxide layer, second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer.

Abstract translation: 在一个实施例中，本发明涉及一种形成NAND型快闪存储器件的方法，包括以下步骤：在衬底的至少一部分上生长第一氧化物层，所述衬底包括闪存单元区域和选择栅极 区; 去除衬底的闪存单元区域中的第一氧化物层的一部分; 在所述闪存单元区域中的所述衬底的至少一部分上以及所述选择栅极区域中的第一氧化物层的至少一部分上生长第二氧化物层; 在所述第二氧化物层的至少一部分上沉积第一原位掺杂非晶硅层，所述第一原位掺杂非晶硅层具有约400至约1,000的厚度; 在第一原位掺杂非晶硅层的至少一部分上沉积介电层; 在介电层的至少一部分上沉积第二掺杂非晶硅层; 以及在所述衬底的所述闪存单元区域中形成闪存单元，并在所述选择栅极区域衬底中形成选择栅极晶体管，所述闪存单元包括所述第二氧化物层，所述第一原位掺杂非晶硅层，所述介电层， 以及所述第二掺杂非晶硅层，以及所述选择栅极晶体管包括所述第一氧化物层，第二氧化物层，所述第一原位掺杂非晶硅层，所述介电层和所述第二掺杂非晶硅层。

公开(公告)号：EP0819308B1

公开(公告)日：1999-06-09

申请号：EP95943963.9

申请日：1995-12-22

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HADDAD, Sameer ,  FANG, Hao

IPC: G11C16/06

CPC classification number: G11C16/3477 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3427 ,  G11C16/3486 ,  G11C2216/16 ,  G11C2216/18

Abstract: There is provided an improved method for bulk (or byte) programming an array of flash EEPROM memory cells. A negative voltage is applied to the substrate of the array. A reference voltage of zero volts is applied simultaneously to the drain regions of selected memory cells that are to be programmed. There is also applied simultaneously the same reference voltage of zero volts to the control gates of the selected memory cells. The present invention provides for low current consumption and fast programming of the memory cell, which require only a single, low voltage power supply. The endurance reliability is greater than 100,000 cycles.

公开(公告)号：EP1074046B1

公开(公告)日：2008-08-20

申请号：EP99906961.0

申请日：1999-02-11

Applicant: ADVANCED MICRO DEVICES, INC. ,  FUJITSU LIMITED

Inventor： WANG, John, Jianshi ,  FANG, Hao ,  HIGASHITANI, Masaaki

IPC: H01L21/8247 ,  H01L27/115 ,  H01L21/768

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524

公开(公告)号：EP1218938A1

公开(公告)日：2002-07-03

申请号：EP00948725.7

申请日：2000-07-14

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： CHANG, Kent, Kuohua ,  AU, Kenneth, Wo-Wai ,  FANG, Hao

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11521 ,  H01L27/11524

Abstract: The present invention provides a method and a NAND-type flash memory device. The method includes forming a select gate oxide layer in a select transistor area of a substrate and a tunnel oxide layer in a memory cell area of the substrate; forming a doped amorphous silicon layer on the select gate oxide layer and the tunnel oxide layer, the doped amorphous silicon layer having a dopant level which simultaneously avoids a select transistor word line high resistance problem and a charge gain/charge loss problem; forming an insulating layer on the doped amorphous silicon layer; forming a control gate layer on the insulating layer; and etching at least the doped amorphous silicon layer, the insulating layer, and the control gate layer to form at least one memory cell stack structure and at least one select transistor stack structure. In a preferred embodiment, the polysilicon layer which forms both the floating gate of the flash memory cell and the select gate of the select transistor of the device is doped with between approximately 5 x 1018 and 8 x 1019 ions/cm3 of phosphorus. With this dopant level, the contact resistance of the select transistor's control gate is low, thus keeping the word line resistivity of the device low. Simultaneously, contamination of the tunnel oxide of the flash memory cell by the dopant is limited, allowing for the interface between the floating gate and the tunnel oxide to be smooth, which prevents charge gain/loss problems. Thus, the reliability of the device is increased.

公开(公告)号：EP0819308A1

公开(公告)日：1998-01-21

申请号：EP95943963.0

申请日：1995-12-22

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HADDAD, Sameer ,  FANG, Hao

IPC: G11C16

CPC classification number: G11C16/3477 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3427 ,  G11C16/3486 ,  G11C2216/16 ,  G11C2216/18

Abstract: There is provided an improved method for bulk (or byte) programming an array of flash EEPROM memory cells. A negative voltage is applied to the substrate of the array. A reference voltage of zero volts is applied simultaneously to the drain regions of selected memory cells that are to be programmed. There is also applied simultaneously the same reference voltage of zero volts to the control gates of the selected memory cells. The present invention provides for low current consumption and fast programming of the memory cell, which require only a single, low voltage power supply. The endurance reliability is greater than 100,000 cycles.